darcyrandall2004 Post subject: -119dBc! Posted: Mon May 19, 2008
8:47 am Colonel Joined: Tue Feb 27, 2007 6:16 am
Posts: 46 Hello Its me again, I was reading an application
note that stated that the adjacent channel rejection of a typical pocsag
pager was 65dB at +/-25kHz This places the following restrictions
on the phase noise of my paging transmitter: Assumming a margin
of 10dB, the phase noise must be less than or equal to -65dB - 10log(25kHz/1Hz)
- 10dB = -119dBc/Hz at 25kHz from the Carrier! For a PLL, My
understanding is that the Output phase noise follows that of the crystal
ref for frequencies less than the loop bandwidth and follows that of
the VCO for frequencies greater than the loop bandwidth. Because
the channel spacing is 25kHz, I am going to choose a loop bandiwdth <<
25kHz/10 to avoid problems with reference spurs. Therefore at 25kHz
offset from the carrier, I can assume phase noise output is as a result
of the VCO. Assume I require a VCO that outputs from 440MHz-470MHz.
I believe even a state of the art VCO would have trouble achieving -119dBc
at 25kHz. How then are the big boys producing paging transmitters
with PLL's that meet these requirements? Can someone point me
in the right direction? All I can think of is perhaps they:
1. Use multiple small bandwidth VCO's with low phase noise and switch
in the right one for the correct frequency. 2. Maybe I can design
a low phase noise frequency synth for a lower frequency and then use
a mixer with another low noise oscillator to achieve the correct frequency.
3. Perhaps by using a number of PLL's I could assign the last PLL
a large channel width, and a large loop bandwidth thereby having the
phase noise output still follow the phase noise of a crystal reference.
Do you have any suggestions? Which approach is typically
the easiest and the most common? Your help is very much appreciated
thankyou. _________________ Regards, Darcy Randall, Perth,
Western Australia Top yendori Post subject: Posted:
Tue May 20, 2008 11:43 am General Joined: Thu Sep
25, 2003 1:19 am Posts: 50 Location: texarcana Is the additional
margin really needed? It's my understanding that the phase noise spec
@ 35KHz offset is -105dBc/Hz. I think you can find a VCO to
meet this repeatably. Good Luck, Rod Top
darcyrandall2004 Post subject: Posted: Sat May 24, 2008
4:26 am Colonel Joined: Tue Feb 27, 2007 6:16 am
Posts: 46 If I use two PLL's I can absolutely annihilate the 119dBc
requirement. The first loop has an extremely small bandwidth,
hence phase noise in this loop is predominantly a result of the 120MHz
Crystal VCO. The second loop has an extremely large bandwidth, hence
phase noise in this loop is attributed to the low noise output from
the first loop. I simulated phase noise using typical
values and estimated contribution due to the power supplies.
The problem is either I cant calculate the divider values
to achieve 25kHz channel spacings or it is just not possible.
Does anyone have any suggestions? _________________ Regards,
Darcy Randall, Perth, Western Australia Top darcyrandall2004
Post subject: Posted: Sun May 25, 2008 7:57 am Colonel
Joined: Tue Feb 27, 2007 6:16 am Posts: 46 I solved the
choice of divider values problem. If I use the following parameters
I just might be able to achieve the -119dBc requirement. N1=17600
R1=1023 N2=240 R2=2 Xtal Vco ref 2=3.666666MHz Xtal
Vco ref 1=213125Hz This sets my loop 1 channel bandwidth to
208.3Hz. Any suggestions? _________________ Regards,
Darcy Randall, Perth, Western Australia Top RFDave
Post subject: Posted: Mon May 26, 2008 11:05 am Captain
Joined: Sat Apr 22, 2006 11:14 pm Posts: 10 Hi:
I've got a couple of comments- 1-10 dB of margin is pretty
big, you might want to relax that. 2-Take a look at off the shelf
VCO's. I just took a look at Synergy Microwave, and they have parts
that look like they are close to -115 dBc/Hz phase noise There are
quite a few VCO vendors, you might want to look at the ad's here
on rfcafe. 3-You might want to look at packaged VCO/PLL combinations
as well. 4-I'd look at Fractional-N PLLs. You lock time with a 200
Hz BW is going to be pretty slow. I'm not sure if a paging transmitter
will have the same constraints, but a paging receiver has some pretty
stringent lock time requirements to improve battery life. Dave
Top darcyrandall2004 Post subject: Posted: Mon May
26, 2008 10:43 pm Colonel Joined: Tue Feb 27, 2007
6:16 am Posts: 46 Thanks Dave, Ive just been looking
into fractional synthesizers and I believe they will simply the design.
Cheers _________________ Regards, Darcy Randall, Perth,
Western Australia Top RFDave Post subject: Modulation?Posted:
Wed Jun 04, 2008 10:18 pm Captain Joined: Sat Apr
22, 2006 11:14 pm Posts: 10 How are you planning on doing your
modulation for this? Dave Top darcyrandall2004
Post subject: Posted: Mon Jun 09, 2008 6:48 pm Colonel
Joined: Tue Feb 27, 2007 6:16 am Posts: 46 I was going
to use a technique called two point modulation where I inject the modulation
both on the reference oscillator and the VCO at the same time. I read
that this will remove any restrictions the loop bandiwdth places on
the baud rate I wish to use. _________________ Regards, Darcy
Randall, Perth, Western Australia
Posted 11/12/2012
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