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Latest UHF Data Radio Schematic - RF Cafe Forums

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darcyrandall2004

Post subject: Latest UHF Data Radio Schematic Posted: Mon Sep 08, 2008 8:39 am

Colonel

Joined: Tue Feb 27, 2007 6:16 am

Posts: 46

Hello,

Attached is my latest design for a UHF Data Radio.

This time I have acquired some professional help to answer some of my questions.

The main points that came up regarding my design were:

1. There is not enough filtering, inductors, caps on the power supplies.

2. Remove the 10K resistors feeding the varactors and replace with reactive components. The 10k just adds noise.

3. Instead of simply turning on and off the POWER AMP, I should be using a DAC to adjust the gain over 30ms b4 I turn it on or off. Otherwise switching on and off the AMP places noise on the power supply which in turn modulates the VCO.

4. The filter before the antennae needs to provide an impedance match between the amp and antennae but also it needs to reduce harmonics and spurious emissions below -30dbm. A 2nH inductor at 2.5Amp is not realizable

5. It will be difficult to get the 120MHz crystal to oscillate, instead I should perhaps just buy one off the shelf say from some where like Rakon.

6. My loop bandwidth is so large, it is pointless using Two Point Modulation and in fact the second varactor will only add noise to the VCO.

Please take a look at my design and provide some helpful suggestions.

In particular can anyone reference a decent text that discusses in depth how to go about designing kick arse filtering on the power supplies. Thankyou

I am particularly worried about how I am going to supply a noise free modulating signal to the XTAL reference and the VCO.

Design Notes:

Phase Noise Requirements

According to some documentation I read but now can not find, most pagers provide 65dB adjacent channel rejection for a channel spacing of 25kHz. Using a 10dB margin, at a distance of 25kHz from the carrier, the transmitter must exhibit less than -119dBc Single Side Band Phase Noise.

PLL Design

A large frequency reference oscillator was chosen so that value of "N" could be minimised , hence phase noise could be minimised. Fref = 120MHz.

Inside the loop bandwidth of the PLL, the phase noise follows that of the low noise reference oscillator, outside the loop bandwidth the phase noise follows that of the noisy VCO. A Fractional Synthesizer/PLL was therefore chosen so that the loop bandwidth could be set as large as possible. I chose Analog Devices ADF4154 Fractional Synthesizer. With a value of R=10, The phase comparison frequency works out to be 12MHz. To minimise fractional spurrs, I set the loop bandwidth to be <12/10 MHz, ie 1.2MHz.

The LDO regulators used on the PLL, VCO and Reference oscillator provide about 50dB of PSRR at 25kHz.

The Single SideBand Phase noise for the VCO was obtained from ADS simulations.

I was unable to simulate the Single SideBand Phase noise for the reference oscillator so instead I used the Single SideBand Phase noise or the original oscillator that I later modified for my design

Ktal = 5605Hz/V

KVco=15000000Hz/V

Assuming:

-If I was lucky enough to achieve a constant 80dB PSSR rejection across all frequencies,

-A difficult to achieve 10mV Noise ripple,

-The PLL makes no contribution to the phase noise

-My Matlab code is correct.

The simulated results of Single Side Band Phase Noise

Two point modulation will be used so that baud rate I use is not dependent on the loop bandwidth. Two point modulation will allow signals near DC to be passed with little distortion.

Component values for the OP amps feeding the XTAl ref and VCO were chosen such that the modulating signal would see a flat passband response from the input to the output of the PLL.

Thankyou!

_________________

Regards, Darcy Randall, Perth, Western Australia

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IR

Post subject: Posted: Tue Sep 09, 2008 5:02 pm

Site Admin

Joined: Mon Jun 27, 2005 2:02 pm

Posts: 373

Location: Germany

Hello Darcy,

Well Done!!

There is a known circuit which is used to filter the supply voltage of VCO's.

It is made of an NPN transistor and bypass capacitors of several values (e.g. 10nF, 100nF, 1uF ...depends on the frequency range of the VCO) that are connected at both the NPN's base and collector. The transistor drops the voltage from the supply rail (Vcc) to the voltage level required by the VCO. The emitter is connected to the VCo's supply pin. The only disadvantage is that the Vcc needs to be higher than the VCO's voltage (the drop is the Vce voltage). The NPN's DC operating point is set with voltage divider at the base.

I don't know if it possible to be done in your application.

I will read the rest of your post and provide more feedback if I have.

Good luck!

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darcyrandall2004

Post subject: Posted: Fri Sep 12, 2008 12:36 am

Colonel

Joined: Tue Feb 27, 2007 6:16 am

Posts: 46

Hello,

Thanks, but unfortunately I dont think the transmitter would meet spec in the real world.

Are you referring to using an NPN transitor to perform the biasing of the VCO?

Cheers

_________________

Regards, Darcy Randall, Perth, Western Australia

Top

IR

Post subject: Posted: Fri Sep 12, 2008 6:29 pm

Site Admin

Joined: Mon Jun 27, 2005 2:02 pm

Posts: 373

Location: Germany

Yes, I am referring to that.

You have open questions in the design schematic? do you need answers for them?

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darcyrandall2004

Post subject: Posted: Fri Sep 12, 2008 7:48 pm

Colonel

Joined: Tue Feb 27, 2007 6:16 am

Posts: 46

Hello,

Some of the questions within the schematic already have answers within my first post. Regardless , If you have a different opinion I would be interested to hear it.

I think the biggest problems with the design is the power supply filtering, matching to the antennae and providing the TTL modulating signal. Any comments or text recommendations covering these areas would be greatly appreciated. Cheers

_________________

Regards, Darcy Randall, Perth, Western Australia

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darcyrandall2004

Post subject: Posted: Fri Sep 26, 2008 8:38 am

Colonel

Joined: Tue Feb 27, 2007 6:16 am

Posts: 46

Hello People,

Do you think trying to achieve -119dBc at 25kHz Single Sideband Phase Noise is a realistic and/or necessary target?

I was looking at these specifications for a data radio:

http://www.apollowireless.com/shtml/item/FullPath/2;535;1113/ipid/1113.html

Their radio:

Adjacent Channel Power : < 70dBc

I am thinking this is equivalent to saying their radio is capable of -70dBc at 25kHz Single Sideband Phase Noise. Is my thinking correct?

Thankyou

_________________

Regards, Darcy Randall, Perth, Western Australia

Top

IR

Post subject: Posted: Sun Sep 28, 2008 11:28 am

Site Admin

Joined: Mon Jun 27, 2005 2:02 pm

Posts: 373

Location: Germany

This spec. relates to the relative signal level of the adjacent channel and not to the noise level.

I think that phase noise of -119dBc at 25kHz spacing is not feasible.

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