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PA DC Bias - RF Cafe Forums

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Post subject: PA DC Bias Posted: Tue Feb 13, 2007 4:04 am


Joined: Tue May 02, 2006 4:59 am

Posts: 15


I am looking for information about DC Bias for class A PA.

In LNA i know to design the Q point for best NF.

What are the rules for PA.

let say i am using BJT, what i need to do to design a proper bias.




Post subject: Posted: Tue Feb 13, 2007 5:19 pm


Joined: Fri Feb 02, 2007 5:22 pm

Posts: 5

Location: Overland Park, KS

I believe "technically" for class A you would bias for ID=IDSS/2, but no one really does that at RF since the bias point shifts around with the load and you may not get better linearity compared to a more efficient class AB bias.

As opposed to an LNA, the goal for a PA is to present transistor with a resistive load that allows the maximum possible voltage and current swings (the optimum load line). Of course you'll also need reactance to cancel the output capacitance of the device.

Take a look in Steve Cripps' book "RF Power Amplifiers for Wireless Communications", or "High-Power GaAs FET Amplifiers" edited by John Walker, from which I pulled the following equation for Class A.


Vdgb= gate to drain breakdown voltage (or collector to base for your case)

Vp = pinch off voltage

Vk = knee voltage



Post subject: Posted: Thu Feb 15, 2007 2:42 am


Joined: Tue Mar 15, 2005 11:43 pm

Posts: 65

Location: Singapore

Hi :

I agree with the previous post by madengr. Just added a few considerations in designing bias circuit for PA in particular. (Taking GaAs MESFET, in this explanation).

Generally, for Rg (gate resistance), the considerations for minimum and maximum values are as follow.

1. For Rg minimum value :

Ensure that no negative resistance will occur--> For low frequency stability consideration. It requires Rg to have a sufficient value and the connection to the ground to be short for low frequencies. Connecting Rg close to the gate reduces the connection length to the ground.

1. For Rg maximum value limit:

RgMax= -?Vgs/?IgsMax where



While the biasing length for drain and gate is lambda\4, with DC blocking capacitor. To ensure that at low frequencies, the DC blocking capacitor is an open circuit, the decoupling capacitors are short circuits and the quarter-wavelength line is a very short electrical length.

The details can be found in the following application notes :

http://www.eudyna.com/e/products_e/appl ... cation.pdf

I hope it helps.



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