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darcyrandall2004 Post subject: PLL Design Posted: Sun Feb 24, 2008
12:37 am Colonel Joined: Tue Feb 27, 2007 6:16 am
Posts: 46 Hello, I am attempting to design a POCSAG paging
transmitter. To Ones and zeros are transmitted by sending a
450.325MHz + 4.5kHz signal or a 450.325MHz - 4.5kHz signal.
The channels are broking into 25kHz bands. Correct me if I am
wrong, I need to design a PLL with at least a 9kHz passband.
I am using a LMx2346/2347 PLL from national semiconductor.
Following a text book I have been reading, I have written some code
that will plot the transfer function of the PLL for me. To perform this
correctly, I need to know what the Volts/Rad output of the phase detector
is (the slop of the volts plotted per radians). All I can find with
regards to the phase detector in the datasheet is that the charge pump
will output 4mA max. How do I determine the Volts/Rad output
of the phase detector? Thankyou _________________
Regards, Darcy Randall, Perth, Western Australia Top
IR Post subject: Posted: Mon Feb 25, 2008 6:35 am Site
Admin Joined: Mon Jun 27, 2005 2:02 pm Posts: 373 Location:
Germany Hi Darcy, The current from the charge pump is delivered
to a the loop-filter which converts it to voltage. The current charges
a capacitor which is the first component of the loop filter, as a result
of the constant current flowing through the capacitor a voltage is generated.
Then for the maximal current generated by the phase detector you will
get the maximal voltage. About the bandwidth of loop filter
I guess you are right (As far as I understand) in order to transfer
the full frequency deviation of 9KHz due to the transmission of '0'
and '1'. Top darcyrandall2004 Post subject: Posted:
Wed Feb 27, 2008 12:43 am Colonel Joined: Tue Feb
27, 2007 6:16 am Posts: 46 Hello, The text I am reading
claims that for charge pump PLLs, the phase comparison frequency must
be at least 10 times greater than the PLL bandwidth. My PLL
bandwidth is 9kHz and my phase comparison frequency if 25kHz(the channel
size). I have already laid the board out. Is the above statment from
the text an over simplification or can anyone see a way around this
through design of the loop filter? What other options do I have?
My crystal reference is 10MHz. VCO freq = 450.325MHz. I was
hoping to use an R counter value of 400. A counter = 29, B counter =
562. I am beginning to think that I am going to have to incorporate
a second PLL so that I can achieve stability. Thanks again
_________________ Regards, Darcy Randall, Perth, Western Australia
Top nubbage Post subject: Posted: Wed Feb 27, 2008
7:36 am General Joined: Fri Feb 17, 2006 12:07 pm
Posts: 218 Location: London UK Hi Darcy I think one missing
item of info is the POCSAG signalling rate you are using. Are you using
the bog standard 512bps, or the higher rates sometimes used? An
FSK discrimminator I have used very successfully employed a D type Flip
Flop driven by a crystal clock so that below the clock rate produced
Q=1 (say) and above clock rate produced Q=0, but it sounds like you
are locked into a charge pump circuit. The factor of 10:1 is a rule
of thumb based on assumptions that designers want to use the simplest
loop filter. I believe you can reduce this if you use a more sophisticated
loop filter with high skirt rate roll-off. However, I do not know how
far you can push this. Your system would be nearer 3:1. Top
darcyrandall2004 Post subject: Posted: Wed Feb 27, 2008
5:51 pm Colonel Joined: Tue Feb 27, 2007 6:16 am
Posts: 46 512 bps Cheers _________________ Regards,
Darcy Randall, Perth, Western Australia Top darcyrandall2004
Post subject: Posted: Thu Feb 28, 2008 6:05 pm Colonel
Joined: Tue Feb 27, 2007 6:16 am Posts: 46 Wait, Im confused.
If my N counter value = 32*562 + 29 = 18013, then one input
of the phase detector will see a signal equal to (450.325*10^6+4.5*10^3)/18013
= 25000.250 Hz or for the transmission of a zero, a signal of (450.325*10^6-4.5*10^3)/18013
= 24999.750 Hz. Hence I assume the phase detector output will be a signal
of +/- 0.25Hz and this is the bandwidth I should design the PLL to.
Alternatively because we are transmitting at 512bps, perhaps
I should set my PLL bandwidth to 512Hz. Could someone please
correct my thinking. FYI Baud rate = 512bps, R counter = 400,
N counter =18013, Ref oscillator = 10MHz, TX freq = 450.325*10^6Hz +/-
4.5kHz, Using a charge pump PLL Thankyou again _________________
Regards, Darcy Randall, Perth, Western Australia Top
Peter Raynald Post subject: Posted: Thu Mar 06, 2008 11:25 pm
Captain Joined: Tue Sep 07, 2004 3:09 pm Posts:
11 I think the PLL bandwidth in your case is limited by the baud
rate. I think you need to make sure that your loop bandwidth
is larger than the baud rate by 4 or 5 times. 9KHz seems to me more
than enough. The question or the 10X rule of tumb... I think
it comes from the fact that a PLL is a digital device, you want it to
clock much faster than your filter BW for the gain equation to hold
as it it would all be a nice analog system. However with 25KHz
comparison frequency you will have a nice spur sideband due to your
charge pump leakage unless you have the most brutal filter.
I may not be a concern to you. Top mikerauh Post
subject: Posted: Fri Mar 07, 2008 3:24 pm Lieutenant
Joined: Fri Mar 07, 2008 2:29 pm Posts: 3 Analog Devices has
a great tool available for download on their website. It is called SimPLL.
You can chose different loop filter topologies and see the loop filter
response. The tool also reports modulation bandwidth. The tool is limited
to Analog Devices PLL chips. ADI has many chips, possibly you can find
one with 4 mA output current. Even if not, you can get an idea of what
the 25 kHz reference spurs will be like with a 9 kHz loop BW.
The 10:1 loop filter rule is just a rule of thumb. The problem is
to get enough roll-off in the filter to suppress the reference spurs
while passing the modulation, AND maintaining enough phase margin to
ensure loop stability. You need to know what is the requirement for
reference spur level. Mike Rauh
Posted 11/12/2012
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