Post subject: PLL Phase margin Posted: Sun Oct 14, 2007 6:42
Joined: Tue May 02, 2006 4:59 am
I am looking for good explanation about phase
margin and its relation
to PLL stability.
Why 45 degree is optimum
Thanks in advance,
Post subject: Posted: Tue Oct 16, 2007 12:14 am
Joined: Mon Jun 27, 2005 2:02 pm
Phase margin of 45 deg. is a good compromise between the
lock time of the loop and an adequate loop stability.
margin is defined as 180deg minus the phase of the open loop, at the
frequency of the loop bandwidth.
For detailed explanation about
phase margin and other PLL related topics, you can read in the following
http://www.national.com/appinfo/wireles ... nbook.html