Post subject: Substrate contact Posted: Mon Dec 11, 2006 11:03
Joined: Tue Nov 14, 2006 7:21 pm
In CMOS ckt, there is one extra terminal
for substrate contact to each component.
Can you tell me the
significance of this terminal in CMOS?
what should be the effect
if we avoid this terminal?
Posted: Fri Jan 26, 2007 2:53 am
Fri Jan 26, 2007 2:40 am
Can you tell me the significance
of this terminal in CMOS?
You don't actually have to ground the
terminal but it should at least be tied to the CMOS Source termainal.
The difference in connecting the sub-tie to ground vs. tying it to the
Source would be a slight difference in the threshold voltage.
Of course if we are talking about a PMOS device then the tie would
be connected to either the Source or the positive supply.
should be the effect if we avoid this terminal?
won't work properly.
subject: Posted: Wed Jan 31, 2007 2:22 am
Wed Jun 21, 2006 8:33 pm
Location: Queen Creek, Arizona
In some process technologies, it is possible to avoid connecting
the body, namely specific SOI (Silicon-on-insulator). Here it can also
matter if you are depleted or fully depleted, either way it is defined
by your process.
Generally (especially in a bulk CMOS process),
Jom's statement is correct. If you do not connect it the device will
not function properly.
CMOS RF and Analog