lna Post subject: new to PA design looking for suggestions Posted:
Tue May 05, 2009 11:43 pm Captain Joined: Mon May 04,
2009 6:47 pm Posts: 22 I'm designing a 2W high linearity(>50dBc)
amp for 700MHz application. I'm thinking about freescale's MW6s010N
LDMOS device. I'm really new in PA design so looking for suggestions
1. Will this part be enough for the class A PA design? 2.
How to calculate for the right bias? and efficiency? 3. will
a balanced AB design be a better choice? 4. what substrate would
be suggested? I do have a lot of questions but want to ask aboves
first, thanks. Top IR Post subject: Re: new to
PA design looking for suggestionsPosted: Wed May 06, 2009 4:04 pm
Site Admin Joined: Mon Jun 27, 2005 2:02 pm Posts:
373 Location: Germany Hello, 1. To give a full and more
precise answer to this question, it would be helpful to know your modulation
scheme or if 2W is your average or peak power. 2. You usually
don't need to calculate the bias and efficieny, those are given in the
data sheet for a specific optimized bias point. Working with different
bias, however has a a strong effect on the saturation characterstic
of the PA (P1dB, Psat), as you can notice in Figure 4 on p.5 By increasing
the Ids current the transistor will go slightly sooner into saturation
(i.e. at lower output power) and by decreasing vice versa. 3.
This is highly depend on your modulation scheme and how far you are
from the peak power rating of the device (Back-off). Take into consideration
that balanced amplifier cost more than twice and takes double the current
compared to single ended design. 4. Good substrates for PA design
are those with lower TanD, stable (over frequency) dielectric constant
er (like those manufactured by Rogers Cooperation - RO4350 is one of
a few) and have a good thermal coefficient in order to stand the heat
generated by the transistor. _________________ Best regards,
- IR Top RDO-RF Post subject: Re: new to
PA design looking for suggestionsPosted: Thu May 07, 2009 9:20 am
Captain Joined: Wed Apr 08, 2009 7:53 am Posts:
12 Hello, If you are talking of 2W avg, and if the 50dBc
are for a two tone analysis, with this amplifier you will reach it but
with no margin.. if fact, you will see on the data sheet that for a
two tone test with an Iq=125mA the 5th order imd is around 48dBc.. you
will have to lower the bias point a little bit to make the 5th order
tone be >50dBc (be careful to not lower it too much because your
3rd order imd will increase.. and you donĀ“t want it to be <50dBc)
Any way, your bias tone will be near 125mA so you can see the eff curves
given by freescale to have a good approximation (around 20% for 2W avg)
Regarding to the substrate I agree with IR. Besides Rogers,
Arlon and Taconic also has good substrates (some times, if you need
to save board area, you might want to choose a substrate with a higher
Er than the RO4350) _________________ web: https://www.rdo-labs.com
Top RDO-RF Post subject: Re: new to PA design looking
for suggestionsPosted: Thu May 07, 2009 4:34 pm Captain
Joined: Wed Apr 08, 2009 7:53 am Posts: 12 I forgot to
tell that it will be very important for your design that you have an
accurate temperature compensated bias circuit. And I also forgot
to tell that freescale usually have loadpull data available if you ask
them for it, and perhaps they have the data on 700MHz... Good luck
_________________ web: https://www.rdo-labs.com Top
lna Post subject: Re: new to PA design looking for suggestionsPosted:
Mon May 11, 2009 1:12 pm Captain Joined: Mon May 04,
2009 6:47 pm Posts: 22 Thanks for replies. I think I am going
to choose balanced class AB design. Then more question, To choose
hybrid couplers for the PA, I found it's hard to get a part both with
good insertion loss and amplitude unbalance. For example, Anaren coupler
is good at insertion loss 0.2dB typ but amplitude unbalance of +-0.5dB.
Another verder's coupler has 0.4dB insertion typ and good unbalance
of 0.3dB. I know both are important for a balanced design. However,
would 0.5dB more unbalanced make a big difference for a balanced PA?
BTW, the moduation is 64QAM up to 256QAM. Top
IR Post subject: Re: new to PA design looking for suggestionsPosted:
Mon May 11, 2009 1:28 pm Site Admin Joined: Mon Jun
27, 2005 2:02 pm Posts: 373 Location: Germany I would take
the hybrid coupler which has lower amplitude imbalance. A higher imbalance
would create assymetry in the power combining and would also cause one
of the amplifiers to move towards compression compared to the other
in the input. _________________ Best regards, - IR
Top lna Post subject: Re: new to PA design looking
for suggestionsPosted: Tue May 12, 2009 12:47 am Captain
Joined: Mon May 04, 2009 6:47 pm Posts: 22 Thanks, IR.
I chose one coupler with .3dB amplitude imbalance and 2 degree of
phase imbalance. Here comes another problem-- the PA nonlinearity due
to the coupler imbalance is too high and would cause system performance
degraded by a couple of dB. It's almost impossible to find a part with
very good imbalance in this 700MHz band. Does this mean the balanced
design is not suitable for high order modulation system?
Top IR Post subject: Re: new to PA design looking for suggestionsPosted:
Tue May 12, 2009 1:20 am Site Admin Joined: Mon Jun
27, 2005 2:02 pm Posts: 373 Location: Germany First, can you
elaborate more (With numbers, if possible) how the coupler imbalance
would degrade the linearity so much? Balanced design, if done
correctly, would lead to better linearity performance compared to single-ended
design. One more question to you, which is not clear for me
until now - your 2W output power is it RMS or peak power (PEP)?
_________________ Best regards, - IR Top
lna Post subject: Re: new to PA design looking for suggestionsPosted:
Tue May 12, 2009 1:47 am Captain Joined: Mon May 04,
2009 6:47 pm Posts: 22 2W is average power with PAR of 12dB (1W
from each amplifier). I just did the calculation using .2dB of
amplitude imbalance and 2degree of phase imbalance the PA nonlinearity
is 2% which could degrade system perfomance by 1dB. With worst case
of 0.5dB/3degree it degrades larger than 2dB. I'm going to recheck my
calculation hope there was a mistake. Top IR
Post subject: Re: new to PA design looking for suggestionsPosted: Tue
May 12, 2009 1:54 pm Site Admin Joined: Mon Jun 27,
2005 2:02 pm Posts: 373 Location: Germany OK, let's put the
numbers in your case: Since the data sheet does not includes
curves for 700MHz, I would take the 900MHz as reference. You
will need more than 1W at each device output in order to have 2W at
the output (In order to compensate for the loss of the hybrid coupler).
According to the datasheet, IM3=-52dBc, at the output of the PA you
will have a marginal result of about IM3=-49dBc with Pout=2W (neglecting
the amplitude imbalance of the hybrid coupler). You can optimize
the bias and/or output matching network in order to improve the results.
You also have to consider the batch-to-batch variations. I have
encountered in a big variation in a device input impedance.
As RDO-RF mentioned, it is important to include a temperature compensation
circuit for the Vgs, in order to cope with the thermal runaway of the
device, which leads to increased Ids with temperature. _________________
Best regards, - IR Top lna Post subject:
Re: new to PA design looking for suggestionsPosted: Tue May 26, 2009
5:27 pm Captain Joined: Mon May 04, 2009 6:47 pm Posts:
22 Hi, IR. I got more questions. I got eval board and going
to manually loadpull this device to find the right matching network.
First of all, what's the proper bias current for such a PA ( 2w and
PAR of 12dB)? as low as possible to Class B? When loadpull the
device, what parameter should I look at? P1dB, IM3...? Finally,
when the device is pulled to the right matching, my understanding is
I need to measure the tuner impedance with VNA, but how do I de-embed
the eval board s-para from device reference plane? By ADS? Thanks
Top IR Post subject: Re: new to PA design looking
for suggestionsPosted: Tue May 26, 2009 6:03 pm Site Admin
Joined: Mon Jun 27, 2005 2:02 pm Posts: 373 Location:
Germany Hello, 1) I would recommend to use the mentioned
bias point in the data sheet (Vdd=28V, Idq=125mA). 2) You should
loadpull the device to maximal P1dB. 3) The impedance that your
tuner will measure is the impedance to which you have to match your
transistor at the output. This means that the reference plane is the
tuner's probe. From this point and on your matching network starts and
ends at the transistor's output flange - Zload. The transistor's
data sheet details Zload at different frequencies (p. 8 ). You can design
the matching netowrk with ADS or any other RF simulator. In addition,
with the PA Wizard in ADS, you can comprare the measured load-pull results
with simulation results if you have the non-linear model of the transistor.
_________________ Best regards, - IR Top
lna Post subject: Re: new to PA design looking for suggestionsPosted:
Wed May 27, 2009 12:28 am Captain Joined: Mon May 04,
2009 6:47 pm Posts: 22 Then I'm confused with 2nd and 3rd above.
Maybe a stupid question, I learned that a PA matching should
be different depends on output power. If load pull to max P1dB and design
to that point, and most of time the PA is working on average power,
Does it mean on average power the PA is not matched well? For
the 3rd, all I have is tuners, eval board and DUT, I wonder how I could
apply the tuner impedence to DUT reference plane immediatly. My understanding
is that the DUT is mounted on a PCB with bias and input/output connectors
which connect to tuners. Is there a better way to apply tuner impedence?
Top IR Post subject: Re: new to PA design looking
for suggestionsPosted: Wed May 27, 2009 11:32 am Site Admin
Joined: Mon Jun 27, 2005 2:02 pm Posts: 373 Location:
Germany Frankly, I never used tuner for my PA's, but this is what
I know: Load pull matching can be done for various operating
conditions e.g. efficiency, maximal output power, ACPR etc.
Your PA requirements are on the edge of the device capabilities (Taking
into considerations the loss of the output coupler), therefore, the
matching should be done to this point. It is true that the PA is not
working on this output power most of the time. Besides the output impedance
of the device changes accordingly with the output power and hence the
matching changes accordingly, the load pull result is quite bounded
(The countours are narrow), load pull match is not meant to cover the
entire output power range. The tuner should be placed as close
as possible to the device, in order to minimize errors and/or losses.
The tuners are to be connected through bias-Tees that allow the device
to receive the bias at both ports. Once the load impedance is known,
then you can design a matching network from the device pin (Zout, give
in the data sheet, denoted as Zload) to the load impedance you measured
with the tuner. You can find additional useful information at
the websites of: Maury Microwave https://www.maurymw.com Focus
Microwave https://www.focus-microwaves.com _________________
Best regards, - IR Top lna Post subject:
Re: new to PA design looking for suggestionsPosted: Wed May 27, 2009
5:49 pm Captain Joined: Mon May 04, 2009 6:47 pm Posts:
22 Balanced design just gives better stability, return loss and
3dB higher P1dB, etc. To get best P1dB and gain, the input and output
need to be matched to low impedance, around 3+j2 and 10+j3, respectively.
Please correct me if it is not true. Regarding the reference
plane, there is always connectors and microstrip lines between tuner
and DUT. How do you deembed them? Top IR Post
subject: Re: new to PA design looking for suggestionsPosted: Thu May
28, 2009 12:52 am Site Admin Joined: Mon Jun 27,
2005 2:02 pm Posts: 373 Location: Germany You are right regarding
the Balanced Amplifier, my mistake. my idea is to deembed the
microstrip lines with ADS. You can enter measure their dimensions and
enter it together with the substrate properties to ADS, hopefully you
will get accurate results. Once this is known, you can then measure
the entire set of connector and microstrip line together as a whole
and get the difference (The addition of the connector). I assume that
you have different microstrip lines at the input and at the output so
you have to repeat over this twice. _________________ Best
regards, - IR Top lna Post subject: Re:
new to PA design looking for suggestionsPosted: Wed Jun 03, 2009 11:37
pm Captain Joined: Mon May 04, 2009 6:47 pm Posts:
22 I'm having problems to match the device for the broadband.
I stared using the suggested circuit for 450MHz and try to tweak
it to higher frequency. With a tunner at output, I can get 11dBW P1dB
easily at certain frequency e.g 600MHz, which is close to vender's datasheet
12.6dBW, but 4dB worse at low and high end. And a interesting thing
is that the good P1dB doesn't come with a good S11, just 7dB, whereas
the good S11 (15dB) at 500MHz comes with a P1dB of 5dBW only.
I have tried differnet combinations still not able to improve S11
for whole band. I realized there willbe a trade off between good match
and P1dB. My questions are, 1. for such a broadband, to get a
desired matching, how many dB of P1dB lower than datasheet's is resonalble?
2. Is multistage matching a must? How many stages is good enough
for my case? 3.There is no enough PCB space for microstrip line
match, would it be difficult using lumped elements? 4. I have
no idea to add the vender's data into ADS, any suggestion? 5.
This maybe out of the topic, I'm wondering how much radiation hazard
coming from the eval board when I power it to 10W RF power?
thanks Top lna Post subject: Re: new to PA design
looking for suggestionsPosted: Wed Jun 03, 2009 11:39 pm Captain
Joined: Mon May 04, 2009 6:47 pm Posts: 22 One more question,
I noticed most of these datasheet suggested matching use caps and
microstipe lines only, why not inductors? Top IR
Post subject: Re: new to PA design looking for suggestionsPosted:
Thu Jun 04, 2009 12:48 am Site Admin Joined: Mon
Jun 27, 2005 2:02 pm Posts: 373 Location: Germany For the
following reasons: 1. Inductors have lower Q compared to capacitors,
which means their DC resistance (ESR) will cause losses in the matching
network and hence loss of power. 2)You will need bulky and expensive
inductors that can stand the high currents at the output of the PA.
The microstrip lines are working as series inductors. Capacitors
are much cheaper and can stand high breakdown voltages (for example
0805 package can stand 200V), their Q is tens times higher compared
to inductors. _________________ Best regards, - IR
Top RDO-RF Post subject: Re: new to PA design looking
for suggestionsPosted: Thu Jun 04, 2009 7:50 am Captain
Joined: Wed Apr 08, 2009 7:53 am Posts: 12 For a broader
band response you will have to add several match stages. Like IR said,
it is recommended to use caps instead of inductors, and if you will
have several matching stages, then capacitors like the 100B series form
ATC are the correct choice for a low loos match. If you want
to skip ADS, you can use a 50ohm line from the transistor to the tuner.
Then you can recalculate the matching network just by shifting the smith
chart around the center. Loadpull contours for IMD, P1DB, Gain,
etc are different form each other, you should pull them out form your
PA and find the correct point for your application. And yes, they are
affected by the bias selected for the measurement and they are affected
by the frequency selected for the measurement.. so you will have many
contours for every Iq ans for every frequency.. so perhaps if you don't
have the proper system to pull the data out, just ask the manufacturer,
freescale has a lot not published loadpull data available if you contact
them. Otherwise you can use ADS o MWO to simulate the loadpulling.
_________________ web: https://www.rdo-labs.com Top
lna Post subject: Re: new to PA design looking for suggestionsPosted:
Sun Jun 21, 2009 1:36 pm Captain Joined: Mon May 04,
2009 6:47 pm Posts: 22 I managed to get more space for MS line
matching. So I wonder if there is a rule of thumb for multistep MS line
matching. For example, to match the output 16.9+j12.7 ohm to 50ohm,
normally how many steps would be used? and what is a reasonable step
to step impedance ratio for wideband matching (200MHz bandwidth over
700MHz)? Top IR Post subject: Re: new to PA design
looking for suggestionsPosted: Mon Jun 22, 2009 3:21 pm Site
Admin Joined: Mon Jun 27, 2005 2:02 pm Posts: 373 Location:
Germany As far as I know, there is no rule of thumb for the number
of steps. It is a compromise of the available space on the board (Which
is a function of the substrate's dielectic constant). If the number
of steps is low, then the matching network is sensitive to the lumped
components values and to the tolerances of the step dimensions (in production).
I would say that for the impedance you mentioned, 2 steps would
be enough, with an increment of 10-12 ohm for each step. I never
worked with such a high BW (Highest was 60MHz for PCS or UMTS bands).
Maybe someone else here would be able to shed more light on your question.
_________________ Best regards, - IR Top
lna Post subject: Re: new to PA design looking for suggestionsPosted:
Wed Jul 08, 2009 10:23 pm Captain Joined: Mon May 04,
2009 6:47 pm Posts: 22 Hi there, I hope I could get a answer
from someone here regarding the realationship of IMD3 V.S tone spacing.
On the MW6S010 evalboard, I measured IMD3 of -40dBc at 450MHz, with
two tone spacing o.1MHz and each tone power of 5W average. That's fine
meets what the datasheet states that IMD3 should be around -40dBc when
tone spacing is not larger than 1MHz. However, when I increased two
tone spacing to 1MHz, under same test setup, IMD3 droped to 25dBc.
Can anyone help me in understanging this? Top
IR Post subject: Re: new to PA design looking for suggestionsPosted:
Thu Jul 09, 2009 12:59 am Site Admin Joined: Mon
Jun 27, 2005 2:02 pm Posts: 373 Location: Germany Hello,
This is the internal non-linear characteristics of the transistor,
which can be related to the matching and to the bias of the device.
As far as I understood you used Tuner for your design, for what
conditions did you match the transistor? While I would not change
the matching too much once the circuit is already up and running, I
would try to see if a bias change improves something. A slightly different
bias point should change the nature of the distortion. It can of course
lead to a different output power, so you have to be able to compensate
it by changing the input power in order to maintain Pout level.
If this does not help, you may need to consider some kind of linearization
scheme. _________________ Best regards, - IR
Top lna Post subject: Re: new to PA design looking
for suggestionsPosted: Mon Oct 26, 2009 4:38 pm Captain
Joined: Mon May 04, 2009 6:47 pm Posts: 22 Greeting. I came
back to this topic with questions. I changed a suspicious transistor
on the eval with a brand new one and I noticed the Ids is not linear
to gate bias voltage any more. Previous transistor the Ids changes 50~80mA
for every 0.1V change on gate bias from 3.0V to 4.0V. Ids of the new
one could jump to 1A when gate bias is about 3.3V. Bu changing the input
matching I can fix it. The question is , Is this a kind of oscillating
issue? How can I measure stability over band? I know how to do
it for small signal amplifier but no experience on high power.
Posted 11/12/2012
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