Torrance, California – June, 2019 - Nicholas Estella, Edmar Camargo, James Schellenberg
and Lani Bui, all from QuinStar Technology, Torrance, CA, wrote this whitepaper entitled
"High-Efficiency, Ka-band GaN Power Amplifiers" which was presented by Mr. Estella
at IMS2019 in Boston, Massachusetts. QuinStar is a California-based microwave and
millimeter-wave engineering company. The works is presented below in its entirety
with permission of QuinStar Technology.
High-Efficiency, Ka-band GaN Power Amplifiers
Nicholas Estella, Edmar Camargo, James Schellenberg and Lani Bui
QuinStar Technology, Inc., Torrance, CA USA
Abstract — This paper reports the design and performance of state-of-the-art GaN
MMICs and a fully packaged Ka-band SSPA. Incorporating harmonic tuning, the MMICs
produce power levels up to 10 W CW with efficiencies in the high thirties (42% peak)
at frequencies of 30 to 34 GHz. These results represent the highest combination
of CW power and efficiency at these frequencies. A 4-way combiner-SSPA, operating
over 31 to 34 GHz, was assembled with these MMICs. Biased at 24 V, this SSPA produced
an output power of greater than 20 W CW with an associated PAE of greater than 30%
across the band. Biased for maximum power at 28 V, it achieved an output power of
32 W CW at 32.5 GHz with an associated PAE of 30%. This is the highest reported
efficiency at this frequency for a packaged amplifier with greater than 30 W CW
Keywords— GaN MMIC, SSPA, power amplifier, Ka-band.
Fig. 1. Small-signal equivalent circuit model for the 8x50 μm
unit cell. Bias: 28 V and Ids = 40 mA (100 mA/mm).
Fig. 2. Measured and simulated results at 30 GHz with pre-matched
8x50 μm unit cell. The test circuit is shown as an insert. Bias: 20 V and Idq=25
Table 1. Stage gate periphery for D1 and D2.
Fig. 3. D1 MMIC (chip size: 5.4 x 3.0 mm2).
Fig. 4. D2 MMIC (chip size: 5.4 x 3.1 mm2).
Fig. 5. On-wafer small-signal performance of D2 compared to simulations.
Bias: Vd=28 V and Id=127 mA (45mA/mm).
Fig. 6. D1 power and efficiency performance at P3dB. Bias:28V.
Fig. 7. D2 power and efficiency performance at P4dB (PSAT). Bias:
Fig. 8. Ka-band SSPA with top half removed. Size: 3.45 x 2.34
x 1.25 in3.
Fig. 9. Power, gain and efficiency of SSPA with Vd=24 V and Pin=20
Table 2. Ka-Band MMIC Benchmarks.
Fig. 10. SSPA output power, gain and efficiency at 32.5 GHz and
Current Ka-band applications, such as point-to-point communications, EW systems,
satellite up and down links and 5G networks, are demanding improvements in power
amplifier efficiency. Deep Space Network (DSN) applications are particularly sensitive
to efficiency due to the limited available prime power. The required power levels
generally range from tens of watts to perhaps several hundred watts with efficiencies
of 30% or more. Using GaN technology, recent work has demonstrated remarkable advancements
in both power and efficiency [1-14]. Single-chip MMICs with output power levels
of up to 40 W pulsed have been demonstrated at 27 GHz with chip efficiencies of
36% . However, no one has reported both high efficiency and high power in a single
chip operating CW. The highest power level MMICs generally have poorer efficiencies
or are operating in a short pulse mode.
This work presents the design and performance of two high efficiency harmonically
tuned Ka-band MMICs. Operating from 29-31 GHz, the first MMIC (called D1) has demonstrated
a peak PAE of 42% with an associated output power of 8 W. The second MMIC (called
D2) has demonstrated power levels of 8-10 W over the 31-34 GHz band with a peak
PAE of 36%.
To the authors’ knowledge, this work represents the highest combination of CW
power and efficiency at 30 GHz for a single GaN chip. Further, a packaged SSPA,
using four D2 MMICs, has demonstrated the best combination of power and efficiency
(32 W and 30% PAE) for a packaged amplifier operating over the 31-34 GHz band.
II. UNIT CELL AND HARMONIC TERMINATIONS
The MMICs reported in this paper were fabricated by Northrop Grumman Aerospace
Systems (NGAS) in Redondo Beach, CA using their GaN20 process (0.2 μm gate length
on 100 μm thick SiC). This process yields a HEMT device with a typical IMAX of 1
A/mm, a breakdown of 90 V and fT and fMAX of 40 and 100 GHz,
respectively. The output power density is typically 4 W/mm for 24-28 V bias.
For the efficiency study, we used an 8x50 μm unit cell, which contains eight
gate fingers, each 50 μm long. The internal source islands are air-bridged over
to the via grounds on both sides. The small-signal equivalent circuit for this cell
is shown in Fig 1. From the model, the fT and fMAX are 41
GHz and 114 GHz respectively.
To investigate the cell matching conditions (fundamental and harmonic) for maximum
efficiency, we performed a series of simulations using the foundry 8x50 μm non-linear
model. The simulations revealed that on the drain side, the device was relatively
insensitive to 2nd harmonic tuning, but it was sensitive to the phase (~180°) of
the 3rd harmonic termination. On the gate side, the opposite was found to be true,
with sensitivity to the 2nd harmonic termination and little sensitivity to the 3rd.
These terminations are similar to what one would expect for inverse Class F operation.
To verify the model results, we fabricated and tested a series of test circuits
(again using the 8x50 μm unit cell) with various combinations of fundamental and
harmonic terminations. The test circuit yielding the best efficiency performance
is shown in Fig. 2, together with its measured and simulated data. In addition to
fundamental matching, this network presents a short circuit to the 2nd harmonic
on the gate side, and a low impedance to the 3rd harmonic on the drain side. Biased
near pinch-off (25 mA/mm) and 20 V, it produced a maximum PAE of 55% (63.3% drain
efficiency) with an associated output power of 29.6 dBm (0.9 W). These results agree
very well with simulation results (also shown) and indicate that harmonic tuning
adds at least 5 percentage points to the efficiency.
III. MMIC DESIGN AND LAYOUT
Based on the simulations and the empirical test cell work, we designed two different
high-efficiency amplifiers: one (called D1) targeting narrowband 30 GHz applications
and the second (D2) for the 31-34 GHz band. Both MMICs use a 3- stage topology and
contain harmonic tuning to enhance efficiency. The device line-up for each MMIC
is summarized in Table 1. The total output gate periphery for D1 and D2 is 2.4 and
1.84 mm respectively.
These two MMICs are shown in Figs. 3 and 4 respectively. With the exception of
the harmonic tuning, the designs are conventional single-ended designs. For simplicity,
we used harmonic tuning only in the final stage, with λ/4 shunt stubs providing
short circuits to the gate at the 2nd harmonic and drain circuits designed to present
a low impedance at the 3rd harmonic. There was no attempt to tune the 2nd harmonic
in the output network.
IV. MMIC MEASUREMENTS
A. Small-Signal Measurements
The MMICs were first characterized on-wafer using a Cascade Microtech probe station
with an Anritsu ME7838D VNA. The small-signal D1 results (23 dB gain centered at
30 GHz) are unremarkable, and hence the plots are omitted. The D2 measurements and
simulations are shown in Fig. 5. The measured gain is typically 27 dB over the 29
to 34 GHz band and compared to the simulation is shifted down in frequency by about
B. Power Measurements
For power evaluation, the MMICs were mounted on a goldplated copper carrier (serving
as the heat sink) and RF probed. For comparison, some MMICs were assembled in Ka-band
test fixtures. The results were similar. The power performance of D1 is illustrated
in Fig. 6. At 3 dB gain compression, the average output power is 38.6 dBm (39.1
dBm peak) between 29 to 31 GHz. The PAE is greater than 38.6% over the 29.5 to 30.5
GHz band and peaks at 42% at 29.5 GHz. The power gain is better than 15 dB over
this same band.
The typical power performance of D2 is plotted in Fig. 7, showing a power ranging
from 39 to 40 dBm (10 W) over the 31 to 34 GHz band, with an associated gain of
24 to 25 dB. The PAE is greater than 30% across the band and reaches a peak of 36%
at 33 GHz.
To put this work in perspective, we summarize the GaN power state-of-the-art
in Table 2. The table is limited to multistage MMIC amplifiers (no single-stage
test circuits) operating above 26.5 GHz. Under the “Test Conditions” column, we
list the operating voltage and whether the results are CW or pulsed. For pulsed
measurements, we list the pulsed conditions (pulse width and duty), if known.
While the table contains several entries at the upper end of Ka-band, most of
the reported results are at or near 30 GHz. The data are listed chronologically
starting in 2012. As expected, the power and efficiency have generally increased
over time. With the exception of one foundry, which uses GaN on Si, all the reported
results employ GaN on SiC substrate, either 100 μm or 50 μm thick. Clearly, the
work reported in this paper represents the highest combination of power and efficiency
for CW operation.
V. KA-BAND SSPA
Based on the performance of D2, we designed and fabricated a 4-way combiner-SSPA
for the 31-34 GHz band. The combiner circuit, shown in Fig. 8, was realized with
binary, 2- tier waveguide H-plane junctions. The back-to-back measured loss (at
34 GHz) of the divider-combiner pair was 0.4 dB or 0.2 dB for each half, including
the loss of the integrated WG-to microstrip transitions. The RF input/output ports
are WR-22 waveguide. The size and weight of this SSPA are 3.45 x 2.34 x 1.25 inch3
(87.6x59.4x31.8 mm3) and 2.2 lbs (1 Kg) respectively.
The SSPA performance, at a reduced bias of 24 V and an input drive level of 20
dBm, is summarized in Fig. 9. It produced an output power of greater than 20 W (24W
peak) with an associated PAE of greater than 30% over the full 31 to 34 GHz band.
The output power is flat at 43.5 dBm ±0.4 dB over this band.
Biased for max power at 28 V, this unit produced a P1dB of 44.5 dBm and a PSAT
of 45.1 dBm (32.4 W) at 32.5 GHz as shown in Fig. 10. As opposed to many GaN amplifiers,
the compression characteristic is very abrupt with the P1dB and the PSAT points
separated by only 0.6 dB. Also, note that the maximum efficiency, 31%, occurs at
or before P1dB, not at PSAT. This characteristic is particularly useful for a linear
amplifier, allowing the SSPA to operate at higher power levels and better efficiencies
without introducing distortion.
This work has established new power and efficiency benchmarks for MMICs operating
at Ka-band frequencies. Utilizing harmonic tuning (2nd and 3rd), we have successfully
demonstrated GaN MMICs producing power levels up to 10 W and efficiencies of over
40% with associated output power levels of 8 W. In contradistinction to many of
the other reported results, these are CW, not pulsed, results. Further, a fully
packaged (waveguide input and output) SSPA has been successfully demonstrated over
the 31 to 34 GHz band, with a peak output power of 32 W and an associated PAE of
This work was supported by NASA under SBIR contract NNX15CP09C.
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