CHYTANYA PARA

312 UTA Blvd, #106
Arlington, TX  76010
Cell Phone: (270) 779-3564
E-mail: chytanyap@gmail.com

(please see letter at bottom)

Objective

Seeking a challenging position in the field of design, development and verification of Analog/digital/RF integrated circuits. My ultimate objective is to make myself stand in parallel with the latest research and developments, and at the same time benefiting the company for which I work.
Education

University of Texas, Arlington, TX - GPA: 3.68 .Expected Graduation Aug 2008
Master of Science in Electrical Engineering
J.N.T.University, Hyderabad, India - GPA: 3.75 May 2004
Bachelor of Technology in Electrical and Electonics Engineering

Relevant Coursework

CMOS Mixed signal IC design, CMOS RF IC design, Radio frequency circuit design, Silicon IC fabrication technology, Digital VLSI Design, Advanced Electronics, Semiconductor Device theory, Wireless communication systems, Digital communications, Micro wave systems engineering, Digital Signal Processing,Statistical pattern recognisation.

Technical Skills

Simulators: ADS, PSpice, Hspice
Full custom design: Cadence-Analog design environment, Spectre RF-Layout, Mentor graphics
Synthesis: XILINX
Physical verification: Hercules
CAD Tool's: ASITIC
Scripting Knowledge: PERL,UNIX
Programming languages: C, VHDL, MATLAB/Simulink

Work Experience
UNIVERSITY OF TEXAS, Arlington, TX
Graduate teaching assistant 01/15/2008-05/31/2008
* Working as a teaching assistant for Silicon IC fabrication course, acting as an educator, grader, helping students in doing lab work which includes mask designing, metal deposition, Lithography etc
* Hand on experience on all clean room equipment used in silicon IC fabrication.

UNIVERSITY OF TEXAS, Arlington, TX
IEEE Mentor 01/20/2007-08/28/2007
* Worked as a mentor for undergraduate students in clarifying their doubts in subjects like Circuit analysis, Control systems and in Matlab and Pspcie

TKR College of engineering and technology, Hyderabad, India
Assistant professor 06/21/2004-11/30/2006
* Taught various subjects in the field of electrical engineering and handled corresponding laboratory sessions successfully.
* Worked as a guide for various projects done by undergraduate students and worked as a faculty convener.

Master’s Projects

1) Designed a phase locked loop(PLL) circuit with Frequency of operation 32MHz and Power consumption < 1
mw and we operated the VCO at twice the data carrier frequency (64Mhz). Tools Used: CADENCE
2) Designed a 3-bit 50 Ms/sec flash analog-to-digital converter (ADC) to achieve demonstrated INL < 0.5LSB,
DNL < 0.5LSB with 5mw power dissipation. Tools Used: CADENCE
3) Designed a 4-bit synchronous FIFO memory architecture which is utilized in data exchange between
processing units with capability of processing data under a 100 MHz clock rate. Tools Used: CADENCE
4) Designed completely integrated 2.4GHz low-power low-phase-noise voltage-controlled oscillator (VCO) in
a standard 0.25µm single-poly, 6-metal mixed-signal CMOS process. The VCO-core draws 1.5mA of current
from a 1.2V supply. Tools Used: CADENCE
5) Designed a stable power amplifier using the large signal spice model at 1.414 GHz center frequency with
gain 5 to 6 dB and frequency band from 1GHz to 2GHz. Tools Used: ADS
6) Designed an integrated 5.8 GHz low voltage and low power LNA circuit in 0.25 µm CMOS process. The
designed LNA requires only a 1 V supply voltage and consumes 4.5mW DC power. Tools Used: CADENCE
7) Designed an Automatic gain control (AGC) circuits using VGA for a homodyne receiver at circuit level to
show how the controller bandwidth influences settling times and modulation distortion. Tools Used: ADS
8) Designed a channel equalizer using MLSE for multi-path channel with BPSK modulation. Incorporate
channel coding in the design to experience coding gain. Tools Used: MATLAB 7.0
9) Designed a simulation reference system for GPDCH subject to Rician flat fading. Design a demodulator for
the fading channel with QPSK modulation. Tools Used: MATLAB 7.0

Activities
* Stood first in the class right from school to under graduation
* Winner of national level technical quiz competition conducted at Bapatla engineering college, INDIA
* Won 2nd prize in paper presentation on the topic “HTS transformers” in the technical symposia conducted at Narasaraopet engineering college, INDIA.


Willing to relocate
Reference provided on request

My name is Chytanya Para I am presently doing Master of Science at University of Texas, Arlington, TX with major in Electrical engineering. I am graduating in August '08 and hence looking for Full-time job. During my course work, I have successfully completed hardware related course projects in VLSI/ Analog/ Digital Electronics/ RF and Microwave Circuit designs/ Wireless Communications/ Digital Communications and I am eager to further implement these concepts in my work.

I have worked on the following projects: LC-VCO Design, Flash type ADC, PLL, low noise amplifier, Synchronous FIFO in Cadence and layout (LVS/DRC match) in Cadence Virtuoso. Design of high frequency power amplifier and design of automatic gain control for homodyne receiver circuit in ADS. And design of a channel equalizer using MLSE for multi-path channel with BPSK modulation, Design of a simulation reference system for GPDCH subject to Rician flat fading. Design a demodulator for the fading channel with QPSK modulation using MATLAB 7.0.

I have worked with various EDA tools like Cadence, ADS, ModelSim, HSPICE, PSPICE, Mentor graphics MATLAB, HDL like VHDL, C and have done project involving intensive layout in Cadence Virtuoso.

At present, I am taking course in statistical pattern recognisation which introduces concepts of different signal pattern recognisation techniques and implement projects in the same.

I bring with myself the ability and passion to work on any type of hardware design issues and hard work. I am on F-1 Student visa and will need sponsoring for full-time positions. I am willing to relocate. Please go through my resume attached with this mail.

Thank You.
Sincerely,
Chytanya Para.