Oiki (Jacky) Wong
(Immigration Status: U.S Citizen)
1615 NW 23rd St, Corvallis, OR
jowong1@engineering.uiuc.edu
815-405-4521

Objective:

• An internship position relating to analog/RF circuit design with communication transceiver applications.
• An internship position relating to high speed ADC/DAC Design.
• An internship position with possibility of chip tapeout.

Area of Interest: Analog and RF IC, System-on-chip, Hardware in Communication, Wireless and Wire-line Communication, Semiconductor Fabrication

Education:
Oregon State University (OSU) (2006—Present)
• Pursuing PhD in Electrical Engineering, Major GPA: 3.86/4.0
• Concentration = Analog and Mixed-Signal IC

University of Wisconsin – Madison (UW) (2004— 2006)
• Master of Science in Electrical Engineering Major GPA: 3.44/4.0
• Concentration = Signal Processing, Communication Systems, VLSI
Project: Improved design of a 32bit binary adder using Han Carlson architecture and Ling algorithm running at 4.5GHz using TSMC 0.18um bulk technology. Key words: Dynamic logic, clock over-drive, charge sharing

University of Illinois – Urbana-Champaign (UIUC) (2002—2004)
• Bachelor of Science in Electrical Engineering, Minor: Math Major GPA: 3.45/4.0
• Concentration = Signal Processing, Communication System

Courses: Analog IC Design, RFIC, Theory and Fabrication of Integrated Circuit Devices, Communication Theory, Wireless Communication, Radio Communication Circuit, High Speed Semiconductor Devices, VLSI Systems Design, Random Process, Advanced DSP, Image Processing, Statistics

Experience:
Research Assistant – Oregon State University Corvallis, OR – Sept 2006 – Present
1. Perform research in area of analog and mixed signal integrated circuits.

Teaching Assistant – Oregon State University Corvallis, OR – Sept 2006 – Present
Course: ENGR 201 – Electrical Fundamentals
ECE 322 – Electronic Circuits
1. Grade homework, lab reports and exams
2. Supervise lab sessions.
3. Hold office hours as needed and answer class related questions via email as needed.

Graduate Technical Intern – Intel Corporation Hillsboro, OR – April 2007—Dec 2007
1. Tape out 2nd order delta-sigma modulator for OFDM signaling in 45nm triple well process.

Graduate Technical Intern – Intel Corporation Hillsboro, OR – May 2006—Aug 2006
6-sigma SRAM design for cache applications:
1. Investigate SRAM scaling leakage current for different sizes, model and sleep mode in 45/32nm technology.
2. Investigate threshold voltage and effective channel length variation on SRAM stability in AC write and solutions to scalability from 45 to 32 nm technology.

Device Engineer Co-op – IBM Corporation Rochester, MN – May 2005—Jan 2006
1. Characterization and bring-up for the XBOX 360 CPU, a high-speed multi-core processor: Gathered and observed chip performance based on various temperatures, voltage, bias current and noise level. Documented test results for client.
2. Hardware/model correlation in 65nm SOI technology: Simulated analog circuitries using PowerSpice for DC, AC, and S-parameters, gathered hardware data from wafers of different corners, modified model parameters to fit hardware data, and simulated device curves to extract various parameters.
3. 90-to-65nm technology migrations process: Modified and simulated in VHDL of test cases for various building blocks, generated noise rules and capacitive loading tables, ran timing test and modified layouts.

Publications:
[1] Pandya G, Chen T, Wong O. Parkhouse D, Selvin E, “Low Voltage Operation and Technology Scaling of Register File and Storage Elements With MPP” DTTC 2007


Academic Projects:
0.8V Tunable 2nd Order Butterworth Filter
Abstract:A 2nd order R-MOSFET-C Butterworh filter with tunable corner frequency was designed to combat against PVT variations. Master-slave tuning technique was used as background tuning and digitally tuned switched capacitor bank was used at power up. To tuned the capacitor bank, a current DAC controlled by a shift register was used.

2-Stage 0.8V Fully Differential CMOS OP-AMP Design
Abstract: Design a transistor level 2-stage fully differential operational amplifier operating at 0.8V using TSMC0.18um technology. The opamp was used as part of a 2nd order R-MOSFET-C Butterworth Filter operating also at 0.8Vdd with 115 KHz corner frequency. The gain is 100dB, 60 degree phase margin, 27MHz bandwidth, and 600mV output swing. Power dissipation is 0.9mW.

Image Rejection Receiver Front-End for Bluetooth Application
Design RF receiver blocks including LNA, mixers, polyphase filter and oscillators. LNA was designed to achieve <2.5dB noise figure with >20dB gain and IIP3 >-12dBm. Mixer was designed to down-convert RF signal to 2MHz IF with 1MHz bandwidth with conversion gain of >3.5dB, noise figure <15dB and IIP3 of at least 15dBm. Oscillator was designed to be voltage controlled for 2.398-2.4815GHz with 1Vpp single-ended swing. Polyphase filter is passive to function within VCO oscillation range.

CDMA Base Station Implementation
Abstract: Implemented a base station for an 8-user CDMA communication system that includes: convolution encoder, interleaver, modulator, summing module, through proper design procedures from architecture level down to transistor level layout. Optimized system performance by manipulating architecture, module and gate design along with transistor sizing and proper floor-planning. Explored various VLSI design techniques and issues.

Semiconductor Fabrication Process
Abstract: Fabricated IC devices such as BJT, MOSFET, diode and capacitor on a 4” silicon wafer with the following processes: oxidation (dry, steam, wet), PR process, photolithography, chemical and plasma etching, ion implantation, metallization and testing and verifications. In addition, follow cleanroom safety rules and chemical hazard in semiconductor processing.

Image Restoration using EM Algorithm and Wavelet De-noising Techniques
Abstract: Image restoration can be seen as two separate operations: image sharpening and image de-noising. Sharpening can be done by inverse filtering, Fourier shrinkage or maximizing the expectation of the original image given the degraded image, E[x| ], using an iterative procedure called Expectation-Maximization (EM). De-noising is done by taking advantage of the large number of zeros wavelet-transformation produces for smooth surfaces. Since noise creates non-smoothness in otherwise smooth areas, once transformed, noise creates many small, non-zero coefficients. Threshold is chosen such that coefficients smaller than the threshold are assumed to be caused by noise. With appropriate threshold, and level of decompositions, wavelet de-noising technique has shown better performance than other de-noising techniques without losing much information.

Awards and Leaderships:
• McHenry County College Phi-Theta-Kappa Honor Society Enhanced Member
• McHenry County College Varsity Women’s Basketball Team Roster
• UIUC College of Engineering Transfer Scholarship Recipient
• UIUC College of Engineering Leadership Award
• Women in Electrical and Computer Engineering (WECE)
•Outreach Chair (2002-2003), President (Fall 03’)
• Society for Women Engineer

Skills:
Software: Advanced Design System (ADS), AutoCAD, Cadence Spectre and Virtuoso, SpectreVerilog, Design Architect, IC Station, Labview, Matlab, Mentor Graphic, PowerSpice, PSPICE, Quicksim, Simulink, Xilinx
Instruments: Oscilloscope, Multimeter, Function Generator, Vector Network Analyzer (VNA), Vector Signal Analyzer (VSA), Logic Analyzer
Programming: C++, Matlab, VHDL, Verilog, Perl
OS: Unix, Windows
License: FAA certified Commercial Pilot Certificate w/ Single, High-performance, Multi-engine and Instrument privilege. Note: Certified Flight Instructor (CFI) Certificate in progress

References:
Professor Kartikeya Mayaram
School of Electrical Engineering & Computer Science
Oregon State University
1148 Kelley Engineering Building
Corvallis, OR 97331-5507
Tel: 541-737-2872
Email: karti@eecs.oregonstate.edu

Michael J. Connell
Sr. Project Manager
Engineering and Technology Service
IBM Corporation
3605 Hwy.52 North
Rochester, MN 55901
Tel: 507-253-2105
Email: connellm@us.ibm.com

Gunjan H. Pandya
Digital Enterprise Group
Intel Corporation
Jones Farm 4, Mail Stop 306
2111 NE 25th Ave
Hillsboro, OR 97124-5961
Tel: 503-712-1741
Email: gunjan.h.pandya@intel.com

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