Copyright: 1996 - 2024
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RF Cafe began life in 1996 as "RF Tools" in an AOL screen name web space totaling
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Below are the old forum threads, including responses to the original posts.
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Post subject: Bias Design Posted: Mon Jul 24, 2006 6:58 pm
Joined: Mon Jul 24, 2006 6:28 pm
I`m currently designing a balanced
low noise amplifier using microstrip lines at 2GHz. Can someone explain
how i determine the capacitance i need for the DC block and also the
RF Choke(Inductance)? I`ve read some articles but i just don't get it.
I`d appreciate any help. Thanks!
Post subject: Posted: Mon Jul 24, 2006 11:47 pm
Joined: Wed Jun 21, 2006 8:33 pm
I am going to take a stab at this one, but to be
honest, more information from you would be helpful as your question
is broad and could be referencing any number of design configurations
RF chokes: The typical use for RF chokes is to support
the biasing network. Ideally you have some resistor feeding the DC bias
to your output or input, and then in some applications an RF choke is
used to further isolate the Biasing circuitry from the RF signals. In
such conditions, you are better off choosing an inductor that is actually
rated for RF choke applications, the size would not matter as much as
your frequency band of interest for isolation. The low frequency effectiveness
of the choke is typically realized by the simple inductance size, while
the high end is limited by the inductors series resonance. Basic answer,
find an inductor that isolates the frequency range you want by the necessary
impedance, and ensure that the self-resonance is high enough to meet
your needs. When I state isolation, what I really mean is that the impedance
seen from your output/input to the biasing network does not load down
your circuit creating insertion loss, power loss, gain loss, etc.
As for DC blocking cap, my only comment is to choose a size that
does two things. Is appropriate for your impedance matching network
and couples enough of the signal of interest (low insertion loss) without
ovcercoupling (if it is a narrowband design). the impedance matching
network is what is most important here.
I wish I could give you
magical equations or something that would help, but your question is
too broad for me to attempt that. Someone else may have better insight.
CMOS RF and Analog ESD Specialist!
Post subject: Posted: Tue Jul 25, 2006 6:08
Joined: Mon Jul 24, 2006 6:28 pm
Thank you for your great insight. Yes i agree
i haven't given enough information on the design. It`s a narrowband
(1.9-2Ghz) balanced amplifier using 3dB branch line couplers with open
circuit stubs for input and output matching to a (BFG425W) BJT Philips
Transistor. The circuit is to be manufactured on RT/Duroid 5880 with
copper conductor. The DC block capacitors will be used so as not to
affect the 50 Ohm chip loads. The biasing will be done by using a quarter
wave length high impedance line with a bypass capacitor to ground to
prevent the short circuit from appearing at the biasing network. Now,
I just want to work out some values for these capacitors to put into
my simulation to get an idea of the overall performance. I`m also toying
with the idea of introcuding biasing just using an inductor as there
may be one commercially available that's suitable. Hope that clears
up things a bit.
Post subject: Bias
DesignPosted: Tue Jul 25, 2006 7:22 am
Fri Feb 17, 2006 12:07 pm
Location: London UK
Choice of inductors and capacitors for bias circuits should
be focussed more on parasitic resonances due to the presence of cap
in an inductor and lead inductance in the bypass cap.
if the reactance of the nominal value is about ten times the circuit
impedance that is OK (often around 15 to 20 ohms on the output side
before the 50 ohm transformer).
The choke and cap manufacturer
data sheets should quote the parasitics or the main parasitic resonant
frequency. This should be just above the max frequency of operation
if possible, or if not then use a damping resitor to reduce the Q.
As an example, for your application and assuming a stray parasitic
capacitance of 1pF for the choke, and a circuit Z of 13 ohms, a choke
of 2 turns of 3mm diameter 3mm long gives about 10nH, which will resonate
at about 1560MHz. That is a rough order of magnitude.
I do not
have details of capacitor lead inductances however.
Post subject: Bias DesignPosted: Tue Jul 25, 2006
Joined: Fri Feb 17, 2006 12:07 pm
Location: London UK
Amplifying a little on that previous
post of mine, the choke example give will have a reactance of about
130 ohms at 2GHz, so 10 times the circuit impedance of 13 ohms.
So why not increase the inductance value? Well, a 6 turn choke of
4mm diameter 6mm long will have an inductance about 93 nH, a reactance
of 1170 ohms at 2GHz, but with the 1pF stray capacitance assumed, would
resonate at 520MHz. Bad news. Above this frequency the bypass would
look more and more like a capacitor in parallel with the existing one,
but with no inductance to act as a choke. At resonance it would look
like a high impedance to ground, which is the opposite of what you really
Hope that helps.
Posted: Tue Jul 25, 2006 2:43 pm
Mon Jun 27, 2005 2:02 pm
What I am usually doing is to follow a simple rule of thumb for
inductors: 10*Zo (Or your load impedance) in the lowest frequency. Of
course that by choosing this value of inductor you should pay attention
to the rated SRF and make sure that it is well above your highest frequency.
How well above? In your case I would say at least 2.4GHz.
Capacitors as mentioned in the previous posts this shouldn't affect
your matching network and cause to insertion loss, so what I usually
do is to choose a coupling capacitor that will cause an impedance of
bwtween 3-5 ohm in the lowest frequency of the band (As the reactance
decreases as frequency becomes higher).
It is a well-known idea
to use quarter wavelength with a bypass capacitor for forming a narrow-band
bypass network, you have to choose the SRF of the capacitor to match
Hope I helped.[/b]