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ESD HBM model Test Bench - RF Cafe Forums
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dkace
Post subject: ESD HBM model Test Bench Posted: Mon Aug 31,
2009 7:33 am
Lieutenant
Joined: Mon Aug 31, 2009 7:25
am
Posts: 1
Hi all,
I am building a HBM ESD test bench
and I came up to the following question:
When I connect the ESD
protection circuit and the theoretical input to the main circuit (ie
an n-MOS),
what I put as Vcc and Vee voltage of the ESD?
My original idea is to leave it floating. But then, floating means arbitrary
voltage in the power lines.
My second thought is to put both
VCC and VEE inputs to the same node which eventually is connected to
the substrate.
The second approach shows a well operating ESD
protection scheme. But is it the correct one, meaning, is it the one
corresponding in the real situation?
Thanks,
D.
Top
Paul Chriss
Post subject: Re: ESD HBM model
Test BenchPosted: Mon Sep 21, 2009 10:33 pm
Captain
Joined:
Sat Mar 04, 2006 10:12 am
Posts: 8
IEC 61000-4-2 lays out all
of the "official" tests for ESD testing.
International Electrotechnical
Commission
Unfortunately, you have to buy the spec from IEC (not
cheap):
http://webstore.iec.ch/webstore/webstore.nsf/artnum/042407
For Military systems, the specification is MIL-STD-883, Method 3015.7
(free, compliments of taxpayers)
http://www.dscc.dla.mil/Downloads/MilSpec/Docs/MIL-STD-883/std883_3000.pdf
Posted
11/12/2012
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