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RF Board PCB Layout - RF Cafe Forums
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IR2712
Post subject: RF Board PCB Layout
Unread postPosted: Mon
Jun 07, 2004 4:06 pm
Hi All,
I am about to enter into
a PCB layout of RF board, which is basically an Up/Down Converter that
operates between 700-2000MHz.
I have few questions regarding
the PCB layout:
1) Supply voltage distribution:
Should
I allocate voltage supply planes in an internal layer of the PCB and
connect these planes to the relevant components through plated via holes?
2) Use of via holes:
The componenet side (Top layer) has
GND plane (all the area which is not used for microstrip traces), should
I connect this GND plane to the internal GND plane with plated via holes
ONLY in the circumference of the board, or in addition to these via
holes should I also add via holes near GND pins of RF components like
Mixers, Couplers LC Filters etc?
The sensitive circuits are in
the down conversion chain, should I avoid routing the voltage planes
beneath these circuits? Should I use traces in the top layer to route
the voltages to the components of thes circuits?
Your inputs
are highly appreciated.
Many thanks
- IR :)
Top
Guest
Post subject:
Unread postPosted: Tue Jun 08,
2004 11:28 am
1) Do NOT use voltage supply planes. They are
a great way for providing leakage between circuits. The inductance of
a series meandering line (sometimes augmented with chokes) is your friend.
This inductance in conjunction with well placed decoupling caps will
decouple your circuits from each other.
Double caps are generally
a bad idea. They will tend to produce a glitch in the decoupling response.
Instead use the largest cap you can get away with.
2) Stitch
the ground planes together with vias at less than .3" spacing. You do
not want significant runs of ground plane not stitched.
Top
IR2712
Post subject:
Unread postPosted: Tue Jun 08,
2004 3:54 pm
Hi,
Many thanks for the input, however I
still have uncleared questions: Do I need to put additional via holes
near RF components beside the stitching in the circumference of the
board?
Many RF devices on the board are Gain Blocks, most manufacturers
of these kind of devices recommend to put a RFC (RF Choke) that will
produce reactance of few hundreds of ohms in the desired frequency band
(lowest frequency of course), bypassed with few values of decoupling
capacitors. You advised not to use several values of capacitors, suppose
I can live with that, but how should I connect these gain blocks to
the same voltage? I need to distribute the voltage to them in some way
and they are scattered all over the board...
:idea:
Many
thanks, I will be happy for more inputs.
- IR
Top
Tony Kurlovich
Post subject:
Unread postPosted: Tue
Jun 08, 2004 4:57 pm
Yes, you should have at least one via very
near each gnd of a component. I meant to stitch vias based on a grid,
not just around the edge.
The use of double caps would be OK
if it weren’t for the small amount of inductance between them (1 to
2nH). Check it out on a simulator or try it in the lab.
The series
inductors are typically chained in series with a cap at the VCC pin
of each device. I generally do not recommend the star arrangement.
Top
Guest
Post subject: Using a large single
capacitor
Unread postPosted: Thu Jun 10, 2004 8:15 am
One
person suggested that using multiple caps is a bad idea. This person
obviously lacks experience in high frequency design. The biggest mistake
that designers make is to use one large capacitor for decoupling thinking
that it will de-couple all frequencies as long as it is large enough.
There is something call "ESR" in capacitors, it is a resonance frequency
where the capacitance is optimum. Below this point you are fine, using
a capacitor above this point and you mine as well put in an inductor.
Use multiple capacitors of various values , including a large value,
to de-couple across the entire frequency band.
Also, place a
minimum of two ground vias as close to the termination of any shunt
component. Remember, that the RF ground is below and vias connect to
the RF ground. Vias also have inductance, the higher the frequency,
the higher the inductive reactance. Using more vias, as close as possible
will minimize this inductance.
Top
Guest 2
Post subject:
Unread postPosted: Thu Jun 10, 2004 12:08 pm
To the above post, I think you mean SRF not ESR for the cap.
All the post I have read hear have metrits to certain applications.
The user must understand a component, there are almost no general
rules for PCB layout. Some components are specifically used at their
SRF.
If good RF work could be summed up in a few rules, then
I am out of a job.
Top
Tony Kurlovich
Post
subject:
Unread postPosted: Thu Jun 10, 2004 12:29 pm
I am
the person that said that double caps in decoupling networks are a bad
idea. I will thank you not to make comments about my experience, which
exceeds 30 years.
Just sweep your double caps and you will find
a parallel resonance in the middle of it all. Try it you might learn
something.
The last time I looked ESR was equivalent series resistance.
It is not a resonance. Caps do have a self-resonance. That is the frequency
above which the reactance is inductive.
Top
Guest
Post subject:
Unread postPosted: Fri Jun 11, 2004 10:09 am
One person doubted that using multiple caps is a bad idea. This
person obviously lacks knowledge in fundamental theory. The Foster’s
theorem claims that the derivative of input impedance is positive function
for any reactive one-port circuit. Which in turn means that between
any two zeros there is pole, and visa versa. By other words, any reactive
one-port circuit which has low input impedance at frequencies f1 and
f2 inevitably has high impedance in-between.
My two backs
Oleg
Top
Tony Kurlovich
Post subject:
Unread postPosted:
Mon Jun 14, 2004 1:48 pm
Well said Oleg.
Good point about
the inverse. The inverse of decoupling is the coupling cap. We don't
see any one paralleling coupling caps because the zero would be immediately
apparent in a wide band circuit.
Top
Ulf Kylenfall
Post subject: PCB's for VHF/UHF
Unread postPosted: Wed Jun 16,
2004 3:09 am
IMHO, the use of both power plane layers and decoupling
capacitors is recommended if it is a multi layer board design. Using
simple traces as supply lines will make them act as microstrip transmission
lines. Also the use of chokes must be verified as a choke together with
a decoupling capacitor will have a resonance somewhere in the spectrum.
If this resonance falls within a multiple of the operating frequency
there will be problems. If you plan to use a choke, make sure that the
Q of the decoupling network is low enough not to cause ringing effects.
Therefore:
Use power planes where possible but make sure
that the ground plane layer is SOLID! with absolutely no slots in it
and place the power plane underneath the GND layer. If the power plane
layer is properly designed, it will act as one very good chip capacitor
with exellent decoupling properties - but only if the connection to
the top (signal layer) is made using very short connections. 1 mm of
trace or via is equivalent to 0.7-1 nH which may be enough to impair
the decoupling function.
Use minimum two via holes per decoupling
capacitor.
Use copper fills all over the top layer, keeping a
distance to the RF traces big enough not to make the copper/trace forming
a co-planar waveguide, since this will result in changes to the caracteristic
impedance of RF traces. Stitch the area fills with via holes so there
is no possibility that any copper could act as a patch antenna.
The use of heat relief tracks between decoupling capacitors and
the copper fill requires special attention. It is best to avoid this
all together, but such boards are often impossible to assemble due to
the amount of heat required during the soldering process.
Then
it is easy enough to specify one trace and work with this, but since
the inductance is 0.7~1nH/mm the series inductance will impair the decoupling
seen over a broad bandwith, so try to use minimum two trace s per capacitor.
Use decoupling capacitors with NP0 material for VHF/UHF if you are
using off the shelf components.
It is recommendable to paralell
a eg 1nF capacitor with a ~27-100pF for VHF/UHF use.
Sure, you
can make use of the series resonance formed by the capacitans and the
internal inductans of the capacitors, but performance change as manufacturers
improve their processes. Never rely fully on such effects although they
may seem clever at first.
For lower frewquency decoupling, use
X5R or X7R material. Do not even consider others as Y5V. Theese materials
are voltage and heavily temperature dependant. Some of the moderns high
efficiency materials also exhibit piezo electric effects and may actually
generate noise if the circuit board placed in a vibrating environment(!)
We used such capacitors in an EL high voltage driver and we could hear
the high voltage oscillator...
8)
Top
IR2712
Post subject:
Unread postPosted: Wed Jun 16, 2004 12:42
pm
I wish to thank you all guys for the useful advice. I will
take it all under consideration in the board layout.
Cheers
- :-D IR
Top
Tony Kurlovich
Post subject:
Unread postPosted: Wed Jun 16, 2004 3:32 pm
You have gotten
a lot of different advice. I suggest Looking at the swept responses
AND nodal impedances of ANY candidate decoupling approach before you
commit the success of your design to it.
While the double cap
is a poor idea, it does not significantly hurt you most of the time
due most decoupling networks being over built. For RF, the VCC plane
is another matter. Given significant complexity and gain it will hurt
you more often than not.
Top
Guest
Post subject:
Double Caps
Unread postPosted: Fri Jun 18, 2004 12:14 pm
You are correct I meant SRF although many vendors will only give you
graph of ESR versus frequency making it so you have to determine the
SRF by finding the lowest resistance. I did not have a problem with
Tonys comments. He said that double caps are OK as long as you are aware
were the resonances are. The problem I had was from the suggestion that
double caps are "bad" and use the biggest cap you can find. This may
be fine at lower frequencies but you will probably have a nice inductor
at the higher frequencies.
Top
Guest
Post
subject: Double Caps
Unread postPosted: Fri Jun 18, 2004 12:18 pm
You are correct I meant SRF although many vendors will only
give you graph of ESR versus frequency making it so you have to determine
the SRF by finding the lowest resistance. I did not have a problem with
Tonys comments. He said that double caps are OK as long as you are aware
where the resonances are. The problem I had was from the suggestion
that double caps are "bad" and use the biggest cap you can find. This
may be fine at lower frequencies but you will probably have a nice inductor
at the higher frequencies.
Posted
11/12/2012
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