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These websites contain information relating to ASIC and FPGA design
including white papers, datasheets, tutorials, and online write-ups.
Achieving Design Security Requirements Using eASIC’s
Technology | easic.com/pdf/WP_0004.pdf
White Paper from
eASIC Corp.
The Art of Successful ASIC Design | opencores.org/articles.cgi/view/10
From Opencores.org by John Bedford Solomon.
ASIC Basics Tutorial | radio-electronics.com/info/data/semicond/asic/asic.php
An overview or tutorial of the basics of the ASIC, its advantages
and disadvantages and a tutorial about the ASIC design process and
the use of an ASIC design service. From Radio-Electronics.com.
ASIC Design at Home | jucs.org/jucs_2_6/asic_design_at_home
From Journal of Universal Computer Science, Heinrichmeyer Friedrich.
ASIC Design Channel | powerdesign365.com/ASIC_design
ASIC design articles, product information and vendors from Power
Design 365.
ASIC Design Guidelines | atmel.com/dyn/resources/prod_documents/doc1205.pdf
Application note from Atmel Corporation.
ASIC Design Tips | doulos.com/knowhow/vhdl_designers_guide/tips
A mix of useful tips from Doulos Ltd.
ASIC Design Methodology Primer | ee.pdx.edu/~greenwd/asic_primer1.pdf
Abstract from IBM.
ASIC-Style Design Techniques for Programmable Devices
| techonline.com/community/tech_topic/timing_closure/36617
By
Salil Raje Hier Design.
ASIC to FPGA Design Methodology & Guidelines
| altera.com/literature/an/an311.pdf
From Altera Corporation.
ASIC Volume Production Without Breaking the Bank
| chipx.com/images/stories/pdf/asic_volume_wp-0404.pdf
Whitepaper
from ChipX, Inc.
Creating a Timing Constraint File for RTL Synthesis Using
the Synplify ASIC® Tool | synplicity.com/literature/pdf/constraint_app_note2.pdf
Application note from Synplicity, Inc.
Design Guidelines for Optimal Results in FPGAs
| altera.com/literature/cp/fpgas-optimal-results-396.pdf
By Jennifer
Stephenson, Altera Corporation.
Design your own ASIC | ap.pennnet.com/Articles/Article_Display.cfm?Section=Articles&Subsection=Display&ARTICLE_ID=185763
From Advanced Packaging, by By Donald Hawk and Kevin Kolwicz.
Embedding the 1-Wire Master | maxim-ic.com/appnotes.cfm/appnote_number/119
Application note from Maxim Integrated Products.
Mixed Signal ASIC Design Methodology for Space Applications
| imse.cnm.es/esd-msd/PUBLIC_DELIV/ABACUS/space-ms.pdf
By L.
Foglia.
Mixed-Signal ASIC Success Story | chipx.com/images/stories/pdf/mixed-signal_asic_successstory.pdf
Whitepaper from ChipX, Inc.
Navigating the Silicon Jungle: FPGA or ASIC?
| chipdesignmag.com/display.php?articleId=115&issueId=11
From Chip Design, by John Blyler.
SideChip ASIC Approach Increases Chip Designers' Flexibility
| chipx.com/images/stories/pdf/sidechip_wp_0241b.pdf
Whitepaper
from ChipX, Inc.
SOI Eases Radiation-Hardened ASIC Designs |
eetimes.com/news/design/showArticle.jhtml?articleID=165700727&printable=true
From EE Times, by Thomas Romanko and Brian Clegg.
Translation Of Existing ASIC Designs | eetasia.com/ARTICLES/2000AUG/2000AUG31_ICD_AN.PDF
From Atmel.
Tutorial 1 - Introduction to ASIC Design Methodology
| ece.ncsu.edu/asic/tutorials/tutor1/tutor1.pdf
This tutorial
is meant only to provide the reader with a brief introduction to
those portions of the design process that occur in the HDL Design
Capture and HDL Design Synthesis phases, and a brief overview of
the design automation tools typically used for these portions of
the design process.
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