Module 13 - Introduction to Number Systems and Logic
Navy Electricity and Electronics Training Series (NEETS)
Chapter 3:  Pages 3-11 through 3-20

Now let's subtract 10₂ from 11₂ using the adder/subtracter circuit. The minuend (11₂) is input on the a terminals, and the subtrahend (10₂) is input on the B terminals. In the subtract mode, a 1 from the control circuit is input to each of the X-OR gates and to the C₀ carry input. By applying a 1 to each of the X-OR gates, you find the output will be the complement of the subtrahend input at B₁  and B₂. Since B₁ is a 0, the output of X-OR 1 will be 1. The input B₂ to X-OR 2 will be inverted to a 0. The High input to C₀ acts as a carry from a previous circuit. The combination of the X-OR gates and the High at C₀ produces the R's complement of the subtrahend. The full adders add the minuend and the R's complement of the subtrahend and produce the difference. The output of C₂ is not used. The outputs of S₂  and S₁  are 0 and 1, respectively, indicating a difference of 01₂. Therefore, 11₂ minus 10₂  equals 01₂.

Q13.   What type of logic gates are added to a parallel adder to enable it to subtract?

Q14.   How many of these gates would be needed to add a four-digit number?

Q15.   In the add mode, what does the output of C₂ indicate?

Q16.   In the subtract mode, a 1 at C₀ performs what portion of the R's complement?

Q17.   In the subtract mode, which portion of the problem is complemented?

FLIP-FLOPS

Flip-flops (FFs) are devices used in the digital field for a variety of purposes. When properly connected, flip-flops may be used to store data temporarily, to multiply or divide, to count operations, or to receive and transfer information.

Flip-flops are bistable multivibrators. The types used in digital equipment are identified by the inputs. They may have from two up to five inputs depending on the type. They are all common in one respect. They have two, and only two, distinct output states. The outputs are normally labeled Q and Q

and should always be complementary. When Q = 1, then Q = 0 and vice versa.

In this section we will discuss four types of FFs that are common to digital equipment. They are the R-S, D, T, and J-K FFs.

R-S FLIP-FLOP

The R-S FF is used to temporarily hold or store information until it is needed. a single R-S FF will store one binary digit, either a 1 or a 0. Storing a four-digit binary number would require four R-S FFs.

The standard symbol for the R-S FF is shown in figure 3-12, view A. The name is derived from the inputs, R for reset and S for set. It is often referred to as an R-S LATCH. The outputs Q and Q are

complements, as mentioned earlier.

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Figure 3-12. - R-S flip-flop: A. Standard symbol; B. R-S FF with inverted inputs.

The R-S FF has two output conditions. When the Q output is High and Q is Low, the FF is set. When Q is Low and  Q is High, the FF is reset. When the R and S inputs are both Low, the Q and Q outputs will both be High. When this condition exists, the FF is considered to be JAMMED and the outputs cannot be used. The jammed condition is corrected when either S or R goes High.

To set the flip-flop requires a High on the S input and a Low on the R input. To reset, the opposite is required; S input Low and R input High. When both R and S are High, the FF will hold or "latch" the condition that existed before both inputs went High.

Because the S input of this FF requires a logic Low to set, a more easily understood symbol is shown in figure 3-12, view B. Refer to this view while reading the following paragraph.

In our description of R-S FF operation, let's assume that the signals applied to the S and R inputs are the LSDs of two different binary numbers. Let's also assume that these two binary numbers represent the speed and range of a target ship. The LSDs will be called SB0 (Speed Bit 0) and RB0 (Range Bit 0) and will be applied to the S and R inputs respectively. Refer to figure 3-12, view B, and figure 3-13. At time T0, both SB0 and RB0 are High, as a result, both Q and Q are High. This is the jammed state and as mentioned earlier, cannot be used in logic circuitry. At T₁, SB0 goes Low and RB0 remains High; Q goes Low and Q remains High; the FF is reset. At T₂  RB0 goes Low and SB0 remains Low; the FF is latched in the reset condition. At T₃, SB0 goes High and RB0 remains Low; the FF sets. At T₄ SB0 goes Low and RB0 goes High; the FF resets. When SB0 and RB0 input conditions reverse at T₅, the FF sets. The circuit is put in the latch condition at T₆ when SB0 goes Low. Notice that the output changes states ONLY when the inputs are in opposite states.

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Figure 3-13. - R-S flip-flop with inverted inputs timing diagram.

Figure 3-14 shows two methods of constructing an R-S FF. We can use these diagrams to prove the

Truth Table for the R-S FF.

Figure 3-14. - R-S FF construction: A. Using cross-coupled Nand gates; B. Using cross-coupled OR gates.

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Look at figure 3-14, view A. Let's assume SB0 is High and RB0 is Low. You should remember from chapter 2 that the output of an inverter is the complement of the input. In this case, since SB0 is High, SBO will be Low. The Low input to Nand gate 1 causes the Q output to go High. This High Q output is also fed to the input of Nand gate 2. The other input to Nand gate 2, RBO, is High. With both inputs to gate 2 High, the output goes Low. The Low Q output is also fed to Nand gate 1 to be used as the "latch" signal. If SB0 goes Low while this condition exists, there will be no change to the outputs because the FF would be in the latched condition; both SB0 and RB0 Low.

When RB0 is High and SB0 is Low, RBO being Low drives the output, Q , to a High condition. The High Q and High SBO inputs to gate 1 cause the output, Q, to go Low. This Low is also fed to Nand gate 2 to be used as the latch signal. Since SB0 is Low, the FF will again go into the latched mode if RB0 goes Low.

The cross-coupled OR gates in figure 3-14, view B, perform the same functions as the Nand gate configuration of view A. a High input at SB0 produces a High Q output, and a Low at RB0 produces a Low Q output. The cross-coupled signals (Q to gate 1 and Q to gate 2) are used as the latch signals just as in view A. You can trace other changes of the inputs using your knowledge of basic logic gates.

Q18.   What are R-S FFs used for?

Q19.   How many R-S FFs are required to store the number 100101₂?

Q20.   For an R-S FF to change output conditions, the inputs must be in what states?

Q21.   How may R-S FFs be constructed?

TOGGLE FLIP-FLOP

The toggle, or T, flip-flop is a bistable device that changes state on command from a common input terminal.

The standard symbol for a T FF is illustrated in figure 3-15, view A. The T input may be preceded by an inverter. An inverter indicates a FF will toggle on a High-to-Low transition of the input pulse. The absence of an inverter indicates the FF will toggle on a Low-to-High transition of the pulse.

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Figure 3-15. - Toggle (T) flip-flop: A. Standard symbol; B. Timing diagram.

The timing diagram in figure 3-15, view B, shows the toggle input and the resulting outputs. We will assume an initial condition (T₀) of Q being Low and Q being High. At T₁, the toggle changes from a Low to a High and the device changes state; Q goes High and Q goes Low. The outputs remain the same at T₂ since the device is switched only by a Low-to-High transition. At T₃, when the toggle goes High, Q goes Low and Q goes High; they remain that way until T₅.

Between T₁ and T₅, two complete cycles of T occur. During the same time period, only one cycle is observed for Q or Q . Since the output cycle is one-half the input cycle, this device can be used to divide the input by 2.

The most commonly used T FFs are J-K FFs wired to perform a toggle function. This use will be demonstrated later in this section.

Q22.   How many inputs does a T FF have?

Q23.   What is the purpose of using T FFs?

D FLIP-FLOP

The D FF is a two-input FF. The inputs are the data (D) input and a clock (CLK) input. The clock is a timing pulse generated by the equipment to control operations. The D FF is used to store data at a predetermined time and hold it until it is needed. This circuit is sometimes called a delay FF. In other words, the data input is delayed up to one clock pulse before it is seen in the output.

The simplest form of a D FF is shown in figure 3-16, view A. Now, follow the explanation of the circuit using the Truth Table and the timing diagram shown in figure 3-16, views B and C.

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Figure 3-16. - D flip-flop: A. Standard symbol; B. Truth Table; C. Timing diagram.

Depending on the circuit design, the clock (CLK) can be a square wave, a constant frequency, or asymmetrical pulses. In this example the clock (CLK) input will be a constant input at a given frequency. This frequency is determined by the control unit of the equipment. The data (D) input will be present when there is a need to store information. Notice in the Truth Table that output Q reflects the D input only when the clock transitions from 0 to 1 (Low to High).

Let's assume that at T₀, CLK is 0, D is 1, and Q is 0. Input D remains at 1 for approximately 2 1/2 clock pulses. At T₁, when the clock goes to 1, Q also goes to 1 and remains at 1 even though D goes to 0 between T₂ and T₃. At T₃, the positive-going pulse of the clock causes Q to go to 0, reflecting the condition of D. The positive-going clock pulse at T₅ causes no change in the output because D is still Low. Between T₅ and T₆, D goes High, but Q remains Low until T₇ when the clock goes High.

The key to understanding the output of the D FF is to remember that the data (D) input is seen in the output only after the clock has gone High.

You may see D FF symbols with two additional inputs ¾ CLR (clear) and PR (preset). These inputs are used to set the start condition of the FF ¾ CLR sets Q to 0; PR sets Q to 1. Figure 3-17 shows the standard symbol with the CLR and PR inputs. Since these inputs are preceded by inverters (part of the FF), a Low-going signal is necessary to activate the FF. These signals (CLR and PR) override any existing condition of the output.

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Figure 3-17. - D flip-flop with PR and CLR inputs.

You may also see an inverter at the clock input. In this case, the output will change on the negative- going transition of the clock pulse.

Q24.   What are the inputs to a D FF?

Q25.   How long is data delayed by a D FF?

Q26.   What condition must occur to have a change in the output of a D FF?

J-K FLIP-FLOP

The J-K FF is the most widely used FF because of its versatility. When properly used it may perform the function of an R-S, T, or D FF. The standard symbol for the J-K FF is shown in view a of figure 3-18.

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Figure 3-18. - J-K flip-flop: A. Standard symbol; B. Truth Table; C. Timing diagram.

The J-K is a five-input device. The J and K inputs are for data. The CLK input is for the clock; and the PS and CLR inputs are the preset and clear inputs, respectively. The outputs Q and Q are the normal complementary outputs.

Observe the Truth Table and timing diagram in figure 3-18, views B and C, as the circuit is explained.

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Line 1 of the Truth Table corresponds to T₀ in the timing diagram. The PS and CLR inputs are both Low. The CLK, J, and K inputs are irrelevant. At this point the FF is jammed, and both Q and Q are High. As with the R-S FF, this state cannot be used.

At T1, PS remains Low while CLR goes High. The Q output remains High and Q goes Low. The FF is in the PRESET condition (line 2 of the Truth Table).

At T₂, PS goes High, CLR goes Low, Q goes Low, and Q goes High. At this point the FF is CLEARED (line 3 of the Truth Table). The condition of the CLK, J, and K inputs have no effect on the PS and CLR actions since these inputs override the other inputs. Starting at T3, PS and CLR will be held at Highs so as not to override the other actions of the FF. Using the PS and CLR inputs only, the circuit

will function as an R-S FF.

Between T₂ and T₃, the CLK input is applied to the device. Since the CLK input has an inverter, all actions will take place on the negative-going transition of the clock pulse.

Line 4 of the Truth Table shows both PS and CLR High, a negative-going CLK, and J and K at 0, or Low. This corresponds to T₃ on the timing diagram. In this condition the FF holds the previous condition of the output. In this case the FF is reset. If the circuit were set when these inputs occurred, it would remain set.

At time T₅, we have a negative-going clock pulse and a High on the J input. This causes the circuit to set, Q to go High, and Q to go Low. See line 5 of the Truth Table.

At T₆, J goes Low, K goes High, and the clock is in a positive-going transition. There is no change in the output because all actions take place on the negative clock transition.

At T₇, when J is Low, K is High; the clock is going negative, the FF resets, Q goes Low, and Q

goes High (line 6).

With both J and K High and a negative-going clock (as at T₉ and line 7), the FF will toggle or change state with each clock pulse. It will continue to toggle as long as J and K both remain High.

Line 8 of the Truth Table indicates that as long as the clock is in any condition other than a negative- going transition, there will be no change in the output regardless of the state of J or K. As mentioned at the beginning of this section, J-K FFs may be used as R-S, T, or D FFs. Figure 3-19 shows how a J-K can be made to perform the other functions.

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Figure 3-19. - J-K versatility: A. Using just the PS and CLR inputs; B. Data applied to the J input; C. Both J and K inputs held High.

In view A, using just the PS and CLR inputs of the J-K will cause it to react like an R-S FF.

In view B, data is applied to the J input. This same data is applied to the K input through an inverter to ensure that the K input is in the opposite state. In this configuration, the J-K performs the same function as a D FF.

View C shows both the J and K inputs held at 1, or High. The FF will change state or toggle with each negative-going transition of the clock just as a T FF will.

Now you can see the versatility of the J-K FF.

Q27.   What type of FF can be used as an R-S, a T, or a D FF?

Q28.   What will be the output of Q if J is High, PS and CLR are High, and the clock is going negative?

Q29.   Assume that K goes High and J goes Low; when will the FF reset?

Q30.   What logic levels must exist for the FF to be toggled by the clock?

Q31.   What two inputs to a J-K FF will override the other inputs?

Q32.   How is the J-K FF affected if PS and CLR are both Low?

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