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Module 13 - Introduction to Number Systems and Logic
Navy Electricity and Electronics Training Series (NEETS)
Chapter 3:  Pages 3-21 through 3-30





Clocks and counters are found in all types of digital equipment. Although they provide different functions, they are all constructed of circuits with which you are familiar. By changing the way the circuits are interconnected, we can build timing circuits, multipliers and dividers, and storage units. In this section we will discuss the purpose, construction, and operation of these important digital circuits.
Clocks have been mentioned in the preceding section with regard to their action with FFs. You will recall that the clock is a timing signal generated by the equipment to control operations. This control feature is demonstrated in both the D and J-K FFs. Remember that the clock output had to be in a certain condition for the FFs to perform their functions.
The simplest form of a clock is the astable or free-running multivibrator. A schematic diagram of a typical free-running multivibrator is shown in figure 3-20 along with its output waveforms. This multivibrator circuit is called free running because it alternates between two different output voltages during the time it is active. Outputs 1 and 2 will be equal and opposite since Q1 and Q2 conduct alternately. The frequency of the outputs may be altered within certain limits by varying the values of R2C1 and R3C2. You may want to review the operation of the astable multivibrator in NEETS, Module 9, Introduction to Wave-Generation and Wave-Shaping Circuits. Although the astable multivibrator circuit seems to produce a good, balanced square wave, it lacks the frequency stability necessary for some types of equipment.


Free-running multivibrator - RF Cafe

Figure 3-20. - Free-running multivibrator.


The frequency stability of the astable multivibrator can be increased by applying a trigger pulse to the circuit. The frequency of the trigger must be higher than the free-running frequency of the multivibrator. The output frequency will match the trigger frequency and produce a more stable output.




Another method of producing a stable clock pulse is to use a triggered monostable or one-shot multivibrator. You will recall from NEETS, Module 9, that a one-shot multivibrator has one stable state and will only change states when acted on by an outside source (the trigger). A block diagram of a monostable multivibrator with input and output signals is shown in figure 3-21. The duration of the output pulse is dependent on the charge time of an RC network in the multivibrator. Each trigger input results in a complete cycle in the output, as shown in figure 3-21. Trigger pulses are supplied by an oscillator.


Monostable multivibrator block diagram - RF Cafe

Figure 3-21. - Monostable multivibrator block diagram.


The circuits described previously are very simple clocks. However, as the complexity of the system increases, so do the timing requirements. Complex systems have multiphase clocks to control a variety of operations. Multiphase clocks allow functions involving more than one operation to be completed during a single clock cycle. They also permit an operation to extend over more than one clock cycle.
A block diagram of a two-phase clock system is shown in figure 3-22, view A. The astable multivibrator provides the basic timing for the circuit, while the one-shot multivibrators are used to shape the pulses. Outputs Q and Q are input to one-shot multivibrators 1 and 2, respectively. The resulting outputs are in phase with the inputs, but the duration of the pulse is greatly reduced as shown in view B.


Two-phase clock: A. Block diagram; B. Timing diagram - RF Cafe

Figure 3-22. - Two-phase clock: A. Block diagram; B. Timing diagram.




Clocks are designed to provide the most efficient operation of the equipment. During the design phase, the frequency, pulse width, and the number of phases required is determined; and the clock circuit is built to meet those requirements.
Most modern high-speed equipment uses crystal-controlled oscillators as the basis for their timing networks. Crystals are stable even at extremely high frequencies.
Q33.   What is a clock with regard to digital equipment?
Q34.   What is the simplest type of clock circuit?
Q35.   What is needed to use a monostable or one-shot multivibrator for a clock circuit?
Q36.   What type of clock is used when more than one operation is to be completed during one clock cycle?

A counter is simply a device that counts. Counters may be used to count operations, quantities, or periods of time. They may also be used for dividing frequencies, for addressing information in storage, or for temporary storage.
Counters are a series of FFs wired together to perform the type of counting desired. They will count up or down by ones, twos, or more.
The total number of counts or stable states a counter can indicate is called MODULUS. For instance, the modulus of a four-stage counter would be 1610, since it is capable of indicating 00002 to 11112. The term modulo is used to describe the count capability of counters; that is, modulo-16 for a four-stage
binary counter, modulo-11 for a decade counter, modulo-8 for a three-stage binary counter, and so forth.
Ripple Counters
Ripple counters are so named because the count is like a chain reaction that ripples through the counter because of the time involved. This effect will become more evident with the explanation of the following circuit.
Figure 3-23, view A, shows a basic four-stage, or modulo-16, ripple counter. The inputs and outputs are shown in view B. The four J-K FFs are connected to perform a toggle function; which, you will recall, divides the input by 2. The HIGHs on the J and K inputs enable the FFs to toggle. The inverters on the clock inputs indicate that the FFs change state on the negative-going pulse.






Four-stage ripple counter: A. Logic diagram; B. Timing diagram - RF Cafe

Figure 3-23. - Four-stage ripple counter: A. Logic diagram; B. Timing diagram.


Assume that A, B, C, and D are lamps and that all the FFs are reset. The lamps will all be out, and the count indicated will be 00002. The negative-going pulse of clock pulse 1 causes FF1 to set. This lights lamp A, and we have a count of 00012. The negative-going pulse of clock pulse 2 toggles FF1, causing it to reset. This negative-going input to FF2 causes it to set and causes B to light. The count after two clock pulses is 00102, or 210. Clock pulse 3 causes FF1 to set and lights lamp A. The setting of FF1 does not affect FF2, and lamp B stays lit. After three clock pulses, the indicated count is 00112.
Clock pulse 4 causes FF1 to reset, which causes FF2 to reset, which causes FF3 to set, giving us a count of 01002. This step shows the ripple effect.
This setting and resetting of the FFs will continue until all the FFs are set and all the lamps are lit. At that time the count will be 11112 or 1510. Clock pulse 16 will cause FF1 to reset and lamp A to go out. This will cause FF2 through FF4 to reset, in order, and will extinguish lamps B, C, and D. The counter would then start at 00012 on clock pulse 17. To display a count of 1610 or 100002, we would need to add another FF.
The ripple counter is also called an ASYNCHRONOUS counter. Asynchronous means that the events (setting and resetting of FFs) occur one after the other rather than all at once. Because the ripple count is asynchronous, it can produce erroneous indications when the clock speed is high. A high-speed clock can cause the lower stage FFs to change state before the upper stages have reacted to the previous clock pulse. The errors are produced by the FFs' inability to keep up with the clock.




Synchronous Counter
High-frequency operations require that all the FFs of a counter be triggered at the same time to prevent errors. We use a SYNCHRONOUS counter for this type of operation.
The synchronous counter is similar to a ripple counter with two exceptions: The clock pulses are applied to each FF, and additional gates are added to ensure that the FFs toggle in the proper sequence.
A logic diagram of a three-state (modulo-8) synchronous counter is shown in figure 3-24, view A. The clock input is wired to each of the FFs to prevent possible errors in the count. A HIGH is wired to the J and K inputs of FF1 to make the FF toggle. The output of FF1 is wired to the J and K inputs of FF2, one input of the AND gate, and indicator A. The output of FF2 is wired to the other input of the AND gate and indicator B. The AND output is connected to the J and K inputs of FF3. The C indicator is the only output of FF3.


Three-stage synchronous counter: A. Logic diagram; B. Timing Diagram - RF Cafe

Figure 3-24. - Three-stage synchronous counter: A. Logic diagram; B. Timing Diagram.


During the explanation of this circuit, you should follow the logic diagram, view A, and the pulse sequences, view B.
Assume the following initial conditions: The outputs of all FFs, the clock, and the AND gate are 0; the J and K inputs to FF1 are HIGH. The negative-going portion of the clock pulse will be used throughout the explanation.
Clock pulse 1 causes FF1 to set. This HIGH lights lamp A, indicating a binary count of 001. The HIGH is also applied to the J and K inputs of FF2 and one input of the AND gate. Notice that FF2 and




FF3 are unaffected by the first clock pulse because the J and K inputs were LOW when the clock pulse was applied.
As clock pulse 2 goes LOW, FF1 resets, turning off lamp A. In turn, FF2 will set, lighting lamp B and showing a count of 0102. The HIGH from FF2 is also felt by the AND gate. The AND gate is not activated at this time because the signal from FF1 is now a LOW. A LOW is present on the J and K inputs of FF3, so it is not toggled by the clock.
Clock pulse 3 toggles FF1 again and lights lamp A. Since the J and K inputs to FF2 were LOW when pulse 3 occurred, FF2 does not toggle but remains set. Lamps A and B are lit, indicating a count of 0112. With both FF1 and FF2 set, HIGHs are input to both inputs of the AND gate, resulting in HIGHs to J and K of FF3. No change occurred in the output of FF3 on clock pulse 3 because the J and K inputs were LOW at the time.
Just before clock pulse 4 occurs, we have the following conditions: FF1 and FF2 are set, and the AND gate is outputting a HIGH to the J and K inputs of FF3. With these conditions all of the FFs will toggle with the next clock pulse.
At clock pulse 4, FF1 and FF2 are reset, and FF3 sets. The output of the AND gate goes to 0, and we have a count of 1002.
It appears that the clock pulse and the AND output both go to 0 at the same time, but the clock pulse arrives at FF3 before the AND gate goes LOW because of the transit time of the signal through FF1, FF2, and the AND gate.
Between pulses 4 and 8, FF3 remains set because the J and K inputs are LOW. FF1 and FF2 toggle in the same sequence as they did on clock pulses 1, 2, and 3.
Clock pulse 7 results in all of the FFs being set and the AND gate output being HIGH. Clock pulse 8 causes all the FFs to reset and all the lamps to turn off, indicating a count of 0002 . The next clock pulse (9) will restart the count sequence.
Q37.   What is the modulus of a five-stage binary counter?
Q38.   An asynchronous counter is also called a                 counter.
Q39.   J-K FFs used in counters are wired to perform what function?
Q40.   What type of counter has clock pulses applied to all FFs?
Q41.   In figure 3-24, view A, what logic element enables FF3 to toggle with the clock?
Q42.   What is the largest count that can be indicated by a four-stage counter?
Decade Counter
A decade counter is a binary counter that is designed to count to 1010, or 10102. An ordinary four- stage counter can be easily modified to a decade counter by adding a NAND gate as shown in figure 3-25. Notice that FF2 and FF4 provide the inputs to the NAND gate. The NAND gate outputs are connected to the CLR input of each of the FFs.






Decade counter - RF Cafe

Figure 3-25. - Decade counter.


The counter operates as a normal counter until it reaches a count of 10102, or 1010. At that time, both inputs to the NAND gate are HIGH, and the output goes LOW. This LOW applied to the CLR input of the FFs causes them to reset to 0. Remember from the discussion of J-K FFs that CLR and PS or PR override any existing condition of the FF. Once the FFs are reset, the count may begin again. The following table shows the binary count and the inputs and outputs of the NAND gate for each count of the decade counter:


Chart - RF Cafe


Changing the inputs to the NAND gate can cause the maximum count to be changed. For instance, if FF4 and FF3 were wired to the NAND gate, the counter would count to 11002  (1210), and then reset.
Q43.   How many stages are required for a decade counter?
Q44.   In figure 3-25, which two FFs must be HIGH to reset the counter?
Ring Counter
A ring counter is defined as a loop of bistable devices (flip-flops) interconnected in such a manner that only one of the devices may be in a specified state at one time. If the specified condition is HIGH,




then only one device may be HIGH at one time. As the clock, or input, signal is received, the specified state will shift to the next device at a rate of 1 shift per clock, or input, pulse.
Figure 3-26, view A, shows a typical four-stage ring counter. This particular counter is composed of R-S FFs. J-K FFs may be used as well. Notice that the output of each AND gate is input to the R, or reset side, of the nearest FF and to the S, or set side, of the next FF. The Q output of each FF is applied to the B input of the AND gate that is connected to its own R input.


Ring counter: A. Logic diagram; B. Timing diagram - RF Cafe

Figure 3-26. - Ring counter: A. Logic diagram; B. Timing diagram.


The circuit input may be normal CLK pulses or pulses from elsewhere in the equipment that would indicate some operation has been completed. Now, let's look at the circuit operation and observe the signal flow as shown in figure 3-26, view B. For an initial condition, let's assume that the output of FF1 is HIGH and that the input and FF2, FF3, and FF4 are LOW. Under these conditions, lamp A will be lit; and lamps B, C, and D will be extinguished. The HIGH from FF1 is also applied to the B input of AND gate 1.
The first input pulse is applied to the A input of each of the AND gates. The B inputs to AND gates 2, 3, and 4 are LOW since the outputs of FF2, FF3, and FF4 are LOW. AND gate 1 now has HIGHs on both inputs and produces a HIGH output. This HIGH simultaneously resets FF1 and sets FF2. Lamp A then goes out, and lamp B goes on. We now have a HIGH on AND gate 2 at the B input. We also have a LOW on AND gate 1 at input B.




Input pulse 2 will produce a HIGH output from AND gate 2 since AND gate 2 is the only one with HIGHs on both inputs. The HIGH from AND gate 2 causes FF2 to reset and FF3 to set. Indicator B goes out and C goes on.
Pulse 3 will cause AND gate 3 to go HIGH. This results in FF3 being reset and FF4 being set. Pulse 4 causes FF4 to reset and FF1 to set, bringing the counter full circle to the initial conditions. As long as the counter is operational, it will continue to light the lamps in sequence - 1, 2, 3, 4; 1, 2, 3, 4, etc.
As we stated at the beginning of this section, only one FF may be in the specified condition at one time. The specified condition shifts one position with each input pulse.
Q45.   In figure 3-26, view A, which AND gate causes FF3 to set?
Q46.   Which AND gate causes FF3 to reset?
Q47.   What causes the specified condition to shift position?
Q48.   If the specified state is OFF, how many FFs may be off at one time?
Down Counters
Up to this point the counters that you have learned about have been up counters (with the exception of the ring counter). An up counter starts at 0 and counts to a given number. This section will discuss DOWN counters, which start at a given number and count down to 0.
Up counters are sometimes called INCREMENT counters. Increment means to increase. Down counters are called DECREMENT counters. Decrement means to decrease.
A three-stage, ripple down counter is shown in figure 3-27, view A. Notice that the PS (preset) input of the J-K FFs is used in this circuit. HIGHs are applied to all the J and K inputs. This enables the FFs to toggle on the input pulses.






Down counter: A. Logic diagram; B. Timing diagram - RF Cafe

Figure 3-27. - Down counter: A. Logic diagram; B. Timing diagram.


A negative-going pulse is applied to all PS terminals to start the countdown. This causes all the FFs to set and also lights indicators A, B, and C. The beginning count is 1112 (710). At the same time, LOWs are applied to the CLK inputs of FF2 and FF3, but they do not toggle because the PS overrides any change. All actions in the counter will take place on the negative-going portion of the input pulse. Let's go through the pulse sequences in figure 3-27, view B.
CP1 causes FF1 to toggle and output Q to go LOW. Lamp A is turned off. Notice that Q goes HIGH
but no change occurs in FF2 or FF3. Lamps B and C are now on, A is off, and the indicated count is 1102 (610).
CP2 toggles FF1 again and lights lamp A. When Q goes HIGH, Q goes LOW. This negative-going signal causes FF2 to toggle and reset. Lamp B is turned off, and a HIGH is felt at the CLK input of FF3. The indicated count is 1012 (510); lamps A and C are on, and B is off.
At CP3, FF1 toggles and resets. Lamp A is turned off. A positive-going signal is applied to the CLK input of FF2. Lamp B remains off and C remains on. The count at this point is 1002 (410).
CP4 toggles FF1 and causes it to set, lighting lamp A. Now FF1, output Q , goes LOW causing FF2 to toggle. This causes FF2 to set and lights lamp B. Output of FF2, Q , then goes LOW, which causes FF3 to reset and turn off lamp C. The indicated count is now 0112 (310).
The next pulse, CP5, turns off lamp A but leaves B on. The count is now 0102. CP6 turns on lamp A and turns off lamp B, for a count of 0012. CP7 turns off lamp A. Now all the lamps are off, and the counter indicates 000.




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